diff options
| author | Jeremy Soller <jeremy@system76.com> | 2022-07-26 08:18:38 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-09-16 16:17:36 +0000 |
| commit | c5d0761dea84b28cd5993b8775a4559974cc8c04 (patch) | |
| tree | cf4154e0dfb7c4baf7bff4ca80600ec87340a6e8 /src | |
| parent | 9601b1e273accfbff816cd6e7627862166cfb472 (diff) | |
soc/intel/cnl: Add Cometlake-H/S Q0 (10+2) CPU ID
The Q0 stepping has a different ID than P1.
Reference: CML EDS Volume 1 (Intel doc #606599)
Change-Id: Id1da42aa93ab3440ae743d943a00713b7df3f453
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/include/cpu/intel/cpu_ids.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/bootblock/report_platform.c | 3 | ||||
| -rw-r--r-- | src/soc/intel/common/block/cpu/mp_init.c | 3 |
3 files changed, 6 insertions, 3 deletions
diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h index bb5511f126..381f20c1ac 100644 --- a/src/include/cpu/intel/cpu_ids.h +++ b/src/include/cpu/intel/cpu_ids.h @@ -44,7 +44,8 @@ #define CPUID_COMETLAKE_H_S_6_2_G0 0xa0650 #define CPUID_COMETLAKE_H_S_6_2_G1 0xa0653 #define CPUID_COMETLAKE_H_S_10_2_P0 0xa0651 -#define CPUID_COMETLAKE_H_S_10_2_Q0_P1 0xa0654 +#define CPUID_COMETLAKE_H_S_10_2_P1 0xa0654 +#define CPUID_COMETLAKE_H_S_10_2_Q0 0xa0655 #define CPUID_TIGERLAKE_A0 0x806c0 #define CPUID_TIGERLAKE_B0 0x806c1 #define CPUID_TIGERLAKE_R0 0x806d1 diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index 578cbbf977..c168431b03 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -33,7 +33,8 @@ static struct { { CPUID_COMETLAKE_H_S_6_2_G0, "Cometlake-H/S G0 (6+2)" }, { CPUID_COMETLAKE_H_S_6_2_G1, "Cometlake-H/S G1 (6+2)" }, { CPUID_COMETLAKE_H_S_10_2_P0, "Cometlake-H/S P0 (10+2)" }, - { CPUID_COMETLAKE_H_S_10_2_Q0_P1, "Cometlake-H/S Q0/P1 (10+2)" }, + { CPUID_COMETLAKE_H_S_10_2_P1, "Cometlake-H/S P1 (10+2)" }, + { CPUID_COMETLAKE_H_S_10_2_Q0, "Cometlake-H/S Q0 (10+2)" }, }; static struct { diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 754c485ba5..d8ca0b3a9a 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -66,7 +66,8 @@ static const struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_6_2_G0 }, { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_6_2_G1 }, { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_10_2_P0 }, - { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_10_2_Q0_P1 }, + { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_10_2_P1 }, + { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_10_2_Q0 }, { X86_VENDOR_INTEL, CPUID_TIGERLAKE_A0 }, { X86_VENDOR_INTEL, CPUID_TIGERLAKE_B0 }, { X86_VENDOR_INTEL, CPUID_TIGERLAKE_R0 }, |