diff options
author | Rex-BC Chen <rex-bc.chen@mediatek.com> | 2021-05-10 19:50:01 +0800 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2021-05-14 09:12:24 +0000 |
commit | c51a54ecddc08187ac9b77498fb8df5b4f82ea1e (patch) | |
tree | 7eb6d19104af0072b73314b57d9b8cbb3a8addd1 /src | |
parent | 5f126a08c8fdd0ed5dc7e02dc084100bde721fb6 (diff) |
mb/google/cherry: Add DRAM calibration support
Initialize and calibrate DRAM in romstage.
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.com>
Change-Id: Ib7677baef126ee60bf35da3a4eaf720eaa118a27
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Diffstat (limited to 'src')
-rw-r--r-- | src/mainboard/google/cherry/Makefile.inc | 3 | ||||
-rw-r--r-- | src/mainboard/google/cherry/boardid.c | 8 | ||||
-rw-r--r-- | src/mainboard/google/cherry/romstage.c | 2 | ||||
-rw-r--r-- | src/mainboard/google/cherry/sdram_configs.c | 15 |
4 files changed, 28 insertions, 0 deletions
diff --git a/src/mainboard/google/cherry/Makefile.inc b/src/mainboard/google/cherry/Makefile.inc index 4720dc586f..a0862d3646 100644 --- a/src/mainboard/google/cherry/Makefile.inc +++ b/src/mainboard/google/cherry/Makefile.inc @@ -7,10 +7,13 @@ verstage-y += chromeos.c verstage-y += reset.c romstage-y += memlayout.ld +romstage-y += boardid.c romstage-y += chromeos.c romstage-y += romstage.c +romstage-y += sdram_configs.c ramstage-y += memlayout.ld +ramstage-y += boardid.c ramstage-y += chromeos.c ramstage-y += mainboard.c ramstage-y += reset.c diff --git a/src/mainboard/google/cherry/boardid.c b/src/mainboard/google/cherry/boardid.c new file mode 100644 index 0000000000..34d7692557 --- /dev/null +++ b/src/mainboard/google/cherry/boardid.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <boardid.h> + +uint32_t ram_code(void) +{ + return 0; +} diff --git a/src/mainboard/google/cherry/romstage.c b/src/mainboard/google/cherry/romstage.c index ec7e4f9a0c..5505d8ac48 100644 --- a/src/mainboard/google/cherry/romstage.c +++ b/src/mainboard/google/cherry/romstage.c @@ -2,6 +2,7 @@ #include <arch/stages.h> #include <soc/clkbuf.h> +#include <soc/emi.h> #include <soc/mt6315.h> #include <soc/mt6359p.h> #include <soc/pmif.h> @@ -15,5 +16,6 @@ void platform_romstage_main(void) mt6315_init(); clk_buf_init(); rtc_boot(); + mtk_dram_init(); scp_rsi_enable(); } diff --git a/src/mainboard/google/cherry/sdram_configs.c b/src/mainboard/google/cherry/sdram_configs.c new file mode 100644 index 0000000000..de6bdd1f05 --- /dev/null +++ b/src/mainboard/google/cherry/sdram_configs.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/dramc_param.h> + +const struct sdram_info *get_sdram_config(void) +{ + /* + * The MT8195 platform supports "dram adaptive" feature to + * automatically detect dram information, including channel, rank, die size..., + * and can automatically configure EMI settings. + * So we will be passing a placeholder param blob. + */ + static struct sdram_info params; + return ¶ms; +} |