diff options
| author | Patrick Rudolph <siro@das-labor.org> | 2017-05-03 17:50:00 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-05-05 23:22:02 +0200 |
| commit | c368620d60d645427da9de26985c2b64eb5bf54d (patch) | |
| tree | 7d16f74d68f07fd80b81f8ae2de13427686f10ef /src | |
| parent | 5c31af8e1afd31c30deb33f65ca3b712b0553552 (diff) | |
sb/intel/bd82x6x/finalize: Use register name
Use register name instead of hex values.
No functional change.
Change-Id: I08fc8435f29ab87a0534946b0e0c43231919785d
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/finalize.c | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pch.h | 1 |
2 files changed, 3 insertions, 2 deletions
diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c index c9296fd949..4e08fc68d3 100644 --- a/src/southbridge/intel/bd82x6x/finalize.c +++ b/src/southbridge/intel/bd82x6x/finalize.c @@ -60,10 +60,10 @@ void intel_pch_finalize_smm(void) RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7)); /* Global SMI Lock */ - pci_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4); + pci_or_config16(PCH_LPC_DEV, GEN_PMCON_1, 1 << 4); /* GEN_PMCON Lock */ - pci_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2)); + pci_or_config8(PCH_LPC_DEV, GEN_PMCON_LOCK, (1 << 1) | (1 << 2)); /* R/WO registers */ RCBA32(0x21a4) = RCBA32(0x21a4); diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 8b22fca334..da1f901f5e 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -140,6 +140,7 @@ early_usb_init (const struct southbridge_usb_port *portmap); #define GEN_PMCON_1 0xa0 #define GEN_PMCON_2 0xa2 #define GEN_PMCON_3 0xa4 +#define GEN_PMCON_LOCK 0xa6 #define ETR3 0xac #define ETR3_CWORWRE (1 << 18) #define ETR3_CF9GR (1 << 20) |