summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorAngel Pons <th3fanbus@gmail.com>2022-02-14 12:39:41 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-02-15 23:37:25 +0000
commitc35ce0e2a6078a083ee36dd533427f2f224457a9 (patch)
tree78ea87c8aff1df64e5638ef1cffd6a4697a632b8 /src
parent4e722d0766d42b76793ca5cff6cfc7be47ecd302 (diff)
nb/intel/ironlake/raminit_heci.c: Turn into compilation unit
Remove the temporary `raminit_heci.c` include and make it a proper compilation unit. Export the `setup_heci_uma()` function. Change-Id: Ia6782a0cb5e731d58764d0fa4ee256bfc8cef98a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src')
-rw-r--r--src/northbridge/intel/ironlake/Makefile.inc1
-rw-r--r--src/northbridge/intel/ironlake/raminit.c3
-rw-r--r--src/northbridge/intel/ironlake/raminit.h2
-rw-r--r--src/northbridge/intel/ironlake/raminit_heci.c2
4 files changed, 4 insertions, 4 deletions
diff --git a/src/northbridge/intel/ironlake/Makefile.inc b/src/northbridge/intel/ironlake/Makefile.inc
index afca10c589..126b6eb5f5 100644
--- a/src/northbridge/intel/ironlake/Makefile.inc
+++ b/src/northbridge/intel/ironlake/Makefile.inc
@@ -11,6 +11,7 @@ ramstage-y += gma.c
romstage-y += memmap.c
romstage-y += raminit.c
+romstage-y += raminit_heci.c
romstage-y += raminit_tables.c
romstage-y += early_init.c
romstage-y += romstage.c
diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c
index 945e139a7b..c6d073ec13 100644
--- a/src/northbridge/intel/ironlake/raminit.c
+++ b/src/northbridge/intel/ironlake/raminit.c
@@ -1503,9 +1503,6 @@ static const struct ram_training *get_cached_training(void)
NULL);
}
-/* TODO: Remove */
-#include "raminit_heci.c"
-
static int have_match_ranks(struct raminfo *info, int channel, int ranks)
{
int ranks_in_channel;
diff --git a/src/northbridge/intel/ironlake/raminit.h b/src/northbridge/intel/ironlake/raminit.h
index edfce51125..05e5ac3ef5 100644
--- a/src/northbridge/intel/ironlake/raminit.h
+++ b/src/northbridge/intel/ironlake/raminit.h
@@ -106,4 +106,6 @@ u16 get_max_timing(struct raminfo *info, int channel);
void early_quickpath_init(struct raminfo *info, const u8 x2ca8);
void late_quickpath_init(struct raminfo *info, const int s3resume);
+void setup_heci_uma(struct raminfo *info);
+
#endif /* RAMINIT_H */
diff --git a/src/northbridge/intel/ironlake/raminit_heci.c b/src/northbridge/intel/ironlake/raminit_heci.c
index 6af1371b51..5c636c946f 100644
--- a/src/northbridge/intel/ironlake/raminit_heci.c
+++ b/src/northbridge/intel/ironlake/raminit_heci.c
@@ -193,7 +193,7 @@ static void send_heci_uma_message(const u64 heci_uma_addr, const unsigned int he
die("HECI init failed\n");
}
-static void setup_heci_uma(struct raminfo *info)
+void setup_heci_uma(struct raminfo *info)
{
if (!info->memory_reserved_for_heci_mb && !(pci_read_config32(HECIDEV, 0x40) & 0x20))
return;