mb/lenovo: add Lenovo ThinkPad X131e (Intel)

The Intel version of ThinkPad X131e can ship with Sandy Bridge or
Ivy Bridge processors.  The mainboard uses 8MiB+4MiB flash chips, with
the 8MiB chip containing the IFD and ME, and the 4MiB chip containing
the BIOS.  The flash chips can be accessed with an external programmer.

This port was primarily created using autoport, with some parts adapted
from lenovo/x230 and google/stout.

Tested and working:
 - Machine type 3367AH5 / Intel Celeron 887 (Sandy Bridge)
 - Boots Debian GNU/Linux 9.2 (Linux 4.9.51) via SeaBIOS
 - Boot from internal SATA and USB
 - Native RAM init
 - Native VGA init
 - libgfxinit
 - VGA and HDMI display output
 - Keyboard, trackpoint, touchpad
 - Audio (speaker, headphones)
 - Ethernet (Realtek)
 - Display backlight
 - USB 3.0 ports
 - "Always on" USB port (EHCI debug)
 - SD card reader
 - Webcam
 - Fan and temperature sensors
 - ACPI S3 (Sleep)
 - CMOS
 - TPM

Not tested:
 - WLAN/Bluetooth (Broadcom)
 - WWAN/mSATA (no card)
 - Other operating systems

Not working or not implemented:
 - Fn keys
 - ACPI S4 (Hibernation) "Image mismatch: memory size"

Change-Id: If8de3a9308997e2d57aee869023ee9a43a2db872
Signed-off-by: James Ye <jye836@gmail.com>
Reviewed-on: https://review.coreboot.org/20694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

18 files changed, 993 insertions, 0 deletions

diff --git a/src/mainboard/lenovo/x131e/Kconfig b/src/mainboard/lenovo/x131e/Kconfig
new file mode 100644
index 0000000000..2341d90d93
--- /dev/null
+++ b/src/mainboard/lenovo/x131e/Kconfig
@@ -0,0 +1,53 @@
+if BOARD_LENOVO_X131E
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select SYSTEM_TYPE_LAPTOP
+	select CPU_INTEL_SOCKET_RPGA989
+	select NORTHBRIDGE_INTEL_SANDYBRIDGE
+	select USE_NATIVE_RAMINIT
+	select SOUTHBRIDGE_INTEL_C216
+	select EC_LENOVO_PMH7
+	select EC_LENOVO_H8
+	select NO_UART_ON_SUPERIO
+	select BOARD_ROMSIZE_KB_12288
+	select HAVE_ACPI_TABLES
+	select HAVE_OPTION_TABLE
+	select HAVE_CMOS_DEFAULT
+	select HAVE_ACPI_RESUME
+	select INTEL_INT15
+	select SANDYBRIDGE_IVYBRIDGE_LVDS
+	select MAINBOARD_HAS_LPC_TPM
+	select MAINBOARD_HAS_LIBGFXINIT
+	select GFX_GMA_INTERNAL_IS_LVDS
+	select SERIRQ_CONTINUOUS_MODE
+
+config HAVE_IFD_BIN
+	bool
+	default n
+
+config MAINBOARD_DIR
+	string
+	default lenovo/x131e
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "ThinkPad X131e"
+
+config MAX_CPUS
+	int
+	default 4
+
+config USBDEBUG_HCD_INDEX
+	int
+	default 2
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+	hex
+	default 0x17aa
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+	hex
+	default 0x21fe
+
+endif # BOARD_LENOVO_X131E
diff --git a/src/mainboard/lenovo/x131e/Kconfig.name b/src/mainboard/lenovo/x131e/Kconfig.name
new file mode 100644
index 0000000000..46cd891397
--- /dev/null
+++ b/src/mainboard/lenovo/x131e/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_LENOVO_X131E
+	bool "ThinkPad X131e"
diff --git a/src/mainboard/lenovo/x131e/Makefile.inc b/src/mainboard/lenovo/x131e/Makefile.inc
new file mode 100644
index 0000000000..7a00ccebd7
--- /dev/null
+++ b/src/mainboard/lenovo/x131e/Makefile.inc
@@ -0,0 +1,18 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+romstage-y += gpio.c
+
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/lenovo/x131e/acpi/ec.asl b/src/mainboard/lenovo/x131e/acpi/ec.asl
new file mode 100644
index 0000000000..02a9d2b66a
--- /dev/null
+++ b/src/mainboard/lenovo/x131e/acpi/ec.asl
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2011 Sven Schnelle <svens@stackframe.org>
+ * Copyright (c) 2017 James Ye <jye836@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define THINKPAD_EC_GPE 22
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
+#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
+#define EC_LENOVO_H8_ME_WORKAROUND 1
+
+#include <ec/lenovo/h8/acpi/ec.asl>
diff --git a/src/mainboard/lenovo/x131e/acpi/platform.asl b/src/mainboard/lenovo/x131e/acpi/platform.asl
new file mode 100644
index 0000000000..9cd327a765
--- /dev/null
+++ b/src/mainboard/lenovo/x131e/acpi/platform.asl
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+	\_SB.PCI0.LPCB.EC.MUTE(1)
+	\_SB.PCI0.LPCB.EC.USBP(0)
+	\_SB.PCI0.LPCB.EC.RADI(0)
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+	/* ME may not be up yet.  */
+	Store (0, \_TZ.MEB1)
+	Store (0, \_TZ.MEB2)
+
+	/* Not implemented.  */
+	Return(Package(){0,0})
+}
diff --git a/src/mainboard/lenovo/x131e/acpi/superio.asl b/src/mainboard/lenovo/x131e/acpi/superio.asl
new file mode 100644
index 0000000000..253a358202
--- /dev/null
+++ b/src/mainboard/lenovo/x131e/acpi/superio.asl
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 James Ye <jye836@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/lenovo/x131e/acpi_tables.c b/src/mainboard/lenovo/x131e/acpi_tables.c
new file mode 100644
index 0000000000..a5d298c26b
--- /dev/null
+++ b/src/mainboard/lenovo/x131e/acpi_tables.c
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/bd82x6x/nvs.h>
+#include "thermal.h"
+
+static void acpi_update_thermal_table(global_nvs_t *gnvs)
+{
+	gnvs->tcrt = CRITICAL_TEMPERATURE;
+	gnvs->tpsv = PASSIVE_TEMPERATURE;
+}
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+	/* Disable USB ports in S3 by default */
+	gnvs->s3u0 = 0;
+	gnvs->s3u1 = 0;
+
+	/* Disable USB ports in S5 by default */
+	gnvs->s5u0 = 0;
+	gnvs->s5u1 = 0;
+
+	/* IGD Displays */
+
+	// the lid is open by default.
+	gnvs->lids = 1;
+
+	acpi_update_thermal_table(gnvs);
+}
diff --git a/src/mainboard/lenovo/x131e/board_info.txt b/src/mainboard/lenovo/x131e/board_info.txt
new file mode 100644
index 0000000000..09ddde1f85
--- /dev/null
+++ b/src/mainboard/lenovo/x131e/board_info.txt
@@ -0,0 +1,6 @@
+Category: laptop
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: n
+Release year: 2012
diff --git a/src/mainboard/lenovo/x131e/cmos.default b/src/mainboard/lenovo/x131e/cmos.default
new file mode 100644
index 0000000000..616420a3bb
--- /dev/null
+++ b/src/mainboard/lenovo/x131e/cmos.default
@@ -0,0 +1,14 @@
+boot_option=Fallback
+debug_level=Spew
+power_on_after_fail=Disable
+nmi=Enable
+volume=0x3
+bluetooth=Enable
+wwan=Enable
+wlan=Enable
+touchpad=Enable
+sata_mode=AHCI
+fn_ctrl_swap=Disable
+sticky_fn=Disable
+trackpoint=Enable
+usb_always_on=Disable
diff --git a/src/mainboard/lenovo/x131e/cmos.layout b/src/mainboard/lenovo/x131e/cmos.layout
new file mode 100644
index 0000000000..35db9ba014
--- /dev/null
+++ b/src/mainboard/lenovo/x131e/cmos.layout
@@ -0,0 +1,129 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+## Copyright (C) 2014 Vladimir Serbinenko
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+# Status Register A
+# -----------------------------------------------------------------
+# Status Register B
+# -----------------------------------------------------------------
+# Status Register C
+#96           4       r       0        status_c_rsvd
+#100          1       r       0        uf_flag
+#101          1       r       0        af_flag
+#102          1       r       0        pf_flag
+#103          1       r       0        irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104          7       r       0        status_d_rsvd
+#111          1       r       0        valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112          8       r       0        diag_rsvd1
+
+# -----------------------------------------------------------------
+0          120       r       0        reserved_memory
+#120        264       r       0        unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384          1       e       4        boot_option
+388          4       h       0        reboot_counter
+#390          2       r       0        unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+#392          3       r       0        unused
+395          4       e       6        debug_level
+#399          1       r       0        unused
+
+#400         8       r       0        reserved for century byte
+
+# coreboot config options: southbridge
+408          1       e       1        nmi
+409          2       e       7        power_on_after_fail
+411          1       e       8        sata_mode
+
+# coreboot config options: EC
+412         1       e       1        bluetooth
+413         1       e       1        wwan
+414         1       e       1        touchpad
+415         1       e       1        wlan
+416         1       e       1        trackpoint
+417         1       e       1        fn_ctrl_swap
+418         1       e       1        sticky_fn
+419         2       e       12       usb_always_on
+#421        3       r       0        unused
+
+# coreboot config options: cpu
+#424        8       r       0        unused
+
+# coreboot config options: northbridge
+432         3        e       11       gfx_uma_size
+#435        5        r       0        unused
+
+440          8       h       0        volume
+
+# SandyBridge MRC Scrambler Seed values
+896         32        r       0        mrc_scrambler_seed
+928         32        r       0        mrc_scrambler_seed_s3
+960         16        r       0        mrc_scrambler_seed_chk
+
+# coreboot config options: check sums
+984         16       h       0        check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+6     1     Emergency
+6     2     Alert
+6     3     Critical
+6     4     Error
+6     5     Warning
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Disable
+7     1     Enable
+7     2     Keep
+8     0     AHCI
+8     1     Compatible
+11    0     32M
+11    1     64M
+11    2     96M
+11    3     128M
+11    4     160M
+11    5     192M
+11    6     224M
+12    0     Disable
+12    1     AC and battery
+12    2     AC only
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 447 984
diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb
new file mode 100644
index 0000000000..ccdff7c6dd
--- /dev/null
+++ b/src/mainboard/lenovo/x131e/devicetree.cb
@@ -0,0 +1,160 @@
+chip northbridge/intel/sandybridge
+	# IGD Displays
+	register "gfx.ndid" = "3"
+	register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"
+
+	register "gpu_dp_d_hotplug" = "0x04"
+
+	# Enable Panel as LVDS and configure power delays
+	register "gpu_panel_port_select" = "0"
+	register "gpu_panel_power_cycle_delay" = "4"
+	register "gpu_panel_power_up_delay" = "100"
+	register "gpu_panel_power_down_delay" = "100"
+	register "gpu_panel_power_backlight_on_delay" = "3000"
+	register "gpu_panel_power_backlight_off_delay" = "2000"
+	register "gfx.use_spread_spectrum_clock" = "1"
+	register "gfx.link_frequency_270_mhz" = "1"
+	register "gpu_cpu_backlight" = "0x1155"
+	register "gpu_pch_backlight" = "0x11551155"
+
+	device cpu_cluster 0x0 on
+		chip cpu/intel/socket_rPGA989
+			device lapic 0x0 on end
+		end
+		chip cpu/intel/model_206ax
+			# Magic APIC ID to locate this chip
+			device lapic 0xacac off end
+
+			register "c1_acpower" = "1"
+			register "c2_acpower" = "3"
+			register "c3_acpower" = "5"
+
+			register "c1_battery" = "1"
+			register "c2_battery" = "3"
+			register "c3_battery" = "5"
+		end
+	end
+
+	register "pci_mmio_size" = "1024"
+
+	device domain 0x0 on
+		subsystemid 0x17aa 0x21fe inherit
+
+		device pci 00.0 on end # Host bridge
+		device pci 01.0 off end # PCIe Bridge for discrete graphics
+		device pci 02.0 on end # Internal graphics VGA controller
+		device pci 04.0 off end # Signal processing controller
+
+		chip southbridge/intel/bd82x6x
+			# GPI routing
+			register "alt_gp_smi_en" = "0x0000"
+			register "gpi6_routing" = "2"
+			register "gpi13_routing" = "2"
+
+			# Enable SATA ports
+			register "sata_port_map" = "0x1"
+			# Set max SATA speed to 6.0 Gb/s
+			register "sata_interface_speed_support" = "0x3"
+
+			register "gen1_dec" = "0x007c1611"
+			register "gen2_dec" = "0x00040069"
+			register "gen3_dec" = "0x000c0701"
+			register "gen4_dec" = "0x000c06a1"
+
+			register "xhci_switchable_ports" = "0xf"
+			register "superspeed_capable_ports" = "0xf"
+			register "xhci_overcurrent_mapping" = "0x00000c03"
+
+			# Enable zero-based linear PCIe root port functions
+			register "pcie_port_coalesce" = "1"
+			register "c2_latency" = "0x0065"
+			register "p_cnt_throttling_supported" = "1"
+
+			register "spi_uvscc" = "0x2005"
+			register "spi_lvscc" = "0x2005"
+
+			device pci 14.0 on end # USB 3.0 Controller
+			device pci 16.0 off end # Management Engine Interface 1
+			device pci 16.1 off end # Management Engine Interface 2
+			device pci 16.2 off end # Management Engine IDE-R
+			device pci 16.3 off end # Management Engine KT
+			device pci 19.0 off end # Intel Gigabit Ethernet
+			device pci 1a.0 on end # USB2 EHCI #2
+			device pci 1b.0 on end # High Definition Audio Audio controller
+			device pci 1c.0 on end # PCIe Port #1
+			device pci 1c.1 on end # PCIe Port #2 (WLAN card)
+			device pci 1c.2 on end # PCIe Port #3 (Card Reader)
+			device pci 1c.3 off end # PCIe Port #4
+			device pci 1c.4 off end # PCIe Port #5
+			device pci 1c.5 on end # PCIe Port #6 (Ethernet controller)
+			device pci 1c.6 off end # PCIe Port #7
+			device pci 1c.7 off end # PCIe Port #8
+			device pci 1d.0 on end # USB2 EHCI #1
+			device pci 1e.0 off end # PCI bridge
+			device pci 1f.0 on # LPC bridge PCI-LPC bridge
+				chip ec/lenovo/pmh7
+					register "backlight_enable" = "0x01"
+					register "dock_event_enable" = "0x00"
+					device pnp ff.1 on end # dummy
+				end
+
+				chip drivers/pc80/tpm
+					device pnp 0c31.0 on end
+				end
+
+				chip ec/lenovo/h8
+					device pnp ff.2 on # dummy
+						io 0x60 = 0x62
+						io 0x62 = 0x66
+						io 0x64 = 0x1600
+						io 0x66 = 0x1604
+					end
+
+					register "config0" = "0xa6"
+					register "config1" = "0x04"
+					register "config2" = "0xa0"
+					register "config3" = "0x62"
+
+					register "has_keyboard_backlight" = "0"
+
+					register "beepmask0" = "0x00"
+					register "beepmask1" = "0x87"
+					register "has_power_management_beeps" = "0"
+
+					register "event0_enable" = "0xff"
+					register "event1_enable" = "0xff"
+					register "event2_enable" = "0xff"
+					register "event3_enable" = "0xff"
+					register "event4_enable" = "0xff"
+					register "event5_enable" = "0xff"
+					register "event6_enable" = "0xff"
+					register "event7_enable" = "0xff"
+					register "event8_enable" = "0xff"
+					register "event9_enable" = "0xff"
+					register "eventa_enable" = "0xff"
+					register "eventb_enable" = "0xff"
+					register "eventc_enable" = "0xff"
+					register "eventd_enable" = "0xff"
+					register "evente_enable" = "0xff"
+					register "eventf_enable" = "0xff"
+				end
+			end
+			device pci 1f.2 on end # SATA Controller 1
+			device pci 1f.3 on # SMBus
+				# eeprom, 8 virtual devices, same chip
+				chip drivers/i2c/at24rf08c
+					device i2c 54 on end
+					device i2c 55 on end
+					device i2c 56 on end
+					device i2c 57 on end
+					device i2c 5c on end
+					device i2c 5d on end
+					device i2c 5e on end
+					device i2c 5f on end
+				end
+			end
+			device pci 1f.5 off end # SATA Controller 2
+			device pci 1f.6 off end # Thermal
+		end
+	end
+end
diff --git a/src/mainboard/lenovo/x131e/dsdt.asl b/src/mainboard/lenovo/x131e/dsdt.asl
new file mode 100644
index 0000000000..b88a813a8e
--- /dev/null
+++ b/src/mainboard/lenovo/x131e/dsdt.asl
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ * Copyright (C) 2014 Vladimir Serbinenko
+ * Copyright (C) 2017 James Ye <jye836@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x03,		// DSDT revision: ACPI v3.0
+	"COREv4",	// OEM id
+	"COREBOOT",	// OEM table id
+	0x20141018	// OEM revision
+)
+{
+	// Some generic macros
+	#include "acpi/platform.asl"
+	#include <cpu/intel/model_206ax/acpi/cpu.asl>
+	#include <southbridge/intel/bd82x6x/acpi/platform.asl>
+
+	// global NVS and variables
+	#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+
+	// Chipset specific sleep states
+	#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+			#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
+			#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+		}
+	}
+}
diff --git a/src/mainboard/lenovo/x131e/gma-mainboard.ads b/src/mainboard/lenovo/x131e/gma-mainboard.ads
new file mode 100644
index 0000000000..698947031f
--- /dev/null
+++ b/src/mainboard/lenovo/x131e/gma-mainboard.ads
@@ -0,0 +1,15 @@
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (HDMI1,
+      Analog,
+      Internal,
+      others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/lenovo/x131e/gpio.c b/src/mainboard/lenovo/x131e/gpio.c
new file mode 100644
index 0000000000..d11b66231c
--- /dev/null
+++ b/src/mainboard/lenovo/x131e/gpio.c
@@ -0,0 +1,213 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 James Ye <jye836@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_GPIO,
+	.gpio1 = GPIO_MODE_GPIO,
+	.gpio2 = GPIO_MODE_GPIO,
+	.gpio3 = GPIO_MODE_GPIO,
+	.gpio4 = GPIO_MODE_GPIO,
+	.gpio5 = GPIO_MODE_GPIO,
+	.gpio6 = GPIO_MODE_GPIO,
+	.gpio7 = GPIO_MODE_GPIO,
+	.gpio8 = GPIO_MODE_GPIO,
+	.gpio12 = GPIO_MODE_GPIO,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio15 = GPIO_MODE_GPIO,
+	.gpio16 = GPIO_MODE_GPIO,
+	.gpio17 = GPIO_MODE_GPIO,
+	.gpio19 = GPIO_MODE_GPIO,
+	.gpio21 = GPIO_MODE_GPIO,
+	.gpio22 = GPIO_MODE_GPIO,
+	.gpio23 = GPIO_MODE_GPIO,
+	.gpio24 = GPIO_MODE_GPIO,
+	.gpio27 = GPIO_MODE_GPIO,
+	.gpio28 = GPIO_MODE_GPIO,
+	.gpio29 = GPIO_MODE_GPIO,
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0 = GPIO_DIR_OUTPUT,
+	.gpio1 = GPIO_DIR_INPUT,
+	.gpio2 = GPIO_DIR_OUTPUT,
+	.gpio3 = GPIO_DIR_OUTPUT,
+	.gpio4 = GPIO_DIR_OUTPUT,
+	.gpio5 = GPIO_DIR_OUTPUT,
+	.gpio6 = GPIO_DIR_INPUT,
+	.gpio7 = GPIO_DIR_INPUT,
+	.gpio8 = GPIO_DIR_OUTPUT,
+	.gpio12 = GPIO_DIR_OUTPUT,
+	.gpio13 = GPIO_DIR_OUTPUT,
+	.gpio15 = GPIO_DIR_INPUT,
+	.gpio16 = GPIO_DIR_OUTPUT,
+	.gpio17 = GPIO_DIR_OUTPUT,
+	.gpio19 = GPIO_DIR_OUTPUT,
+	.gpio21 = GPIO_DIR_OUTPUT,
+	.gpio22 = GPIO_DIR_INPUT,
+	.gpio23 = GPIO_DIR_OUTPUT,
+	.gpio24 = GPIO_DIR_OUTPUT,
+	.gpio27 = GPIO_DIR_INPUT,
+	.gpio28 = GPIO_DIR_OUTPUT,
+	.gpio29 = GPIO_DIR_OUTPUT,
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio0 = GPIO_LEVEL_HIGH,
+	.gpio2 = GPIO_LEVEL_HIGH,
+	.gpio3 = GPIO_LEVEL_HIGH,
+	.gpio4 = GPIO_LEVEL_HIGH,
+	.gpio5 = GPIO_LEVEL_HIGH,
+	.gpio8 = GPIO_LEVEL_LOW,
+	.gpio12 = GPIO_LEVEL_LOW,
+	.gpio13 = GPIO_LEVEL_LOW,
+	.gpio16 = GPIO_LEVEL_HIGH,
+	.gpio17 = GPIO_LEVEL_HIGH,
+	.gpio19 = GPIO_LEVEL_LOW,
+	.gpio21 = GPIO_LEVEL_LOW,
+	.gpio23 = GPIO_LEVEL_LOW,
+	.gpio24 = GPIO_LEVEL_HIGH,
+	.gpio28 = GPIO_LEVEL_HIGH,
+	.gpio29 = GPIO_LEVEL_HIGH,
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_reset = {
+	.gpio24 = GPIO_RESET_RSMRST,
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio1 = GPIO_INVERT,
+	.gpio6 = GPIO_INVERT,
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio33 = GPIO_MODE_GPIO,
+	.gpio34 = GPIO_MODE_GPIO,
+	.gpio35 = GPIO_MODE_GPIO,
+	.gpio36 = GPIO_MODE_GPIO,
+	.gpio37 = GPIO_MODE_GPIO,
+	.gpio38 = GPIO_MODE_GPIO,
+	.gpio39 = GPIO_MODE_GPIO,
+	.gpio40 = GPIO_MODE_GPIO,
+	.gpio41 = GPIO_MODE_GPIO,
+	.gpio48 = GPIO_MODE_GPIO,
+	.gpio49 = GPIO_MODE_GPIO,
+	.gpio51 = GPIO_MODE_GPIO,
+	.gpio53 = GPIO_MODE_GPIO,
+	.gpio54 = GPIO_MODE_GPIO,
+	.gpio57 = GPIO_MODE_GPIO,
+	.gpio59 = GPIO_MODE_GPIO,
+	.gpio60 = GPIO_MODE_GPIO,
+	.gpio61 = GPIO_MODE_GPIO,
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio33 = GPIO_DIR_OUTPUT,
+	.gpio34 = GPIO_DIR_OUTPUT,
+	.gpio35 = GPIO_DIR_OUTPUT,
+	.gpio36 = GPIO_DIR_INPUT,
+	.gpio37 = GPIO_DIR_INPUT,
+	.gpio38 = GPIO_DIR_INPUT,
+	.gpio39 = GPIO_DIR_INPUT,
+	.gpio40 = GPIO_DIR_INPUT,
+	.gpio41 = GPIO_DIR_INPUT,
+	.gpio48 = GPIO_DIR_OUTPUT,
+	.gpio49 = GPIO_DIR_INPUT,
+	.gpio51 = GPIO_DIR_OUTPUT,
+	.gpio53 = GPIO_DIR_OUTPUT,
+	.gpio54 = GPIO_DIR_INPUT,
+	.gpio57 = GPIO_DIR_INPUT,
+	.gpio59 = GPIO_DIR_INPUT,
+	.gpio60 = GPIO_DIR_OUTPUT,
+	.gpio61 = GPIO_DIR_OUTPUT,
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio33 = GPIO_LEVEL_LOW,
+	.gpio34 = GPIO_LEVEL_HIGH,
+	.gpio35 = GPIO_LEVEL_HIGH,
+	.gpio48 = GPIO_LEVEL_LOW,
+	.gpio51 = GPIO_LEVEL_HIGH,
+	.gpio53 = GPIO_LEVEL_HIGH,
+	.gpio60 = GPIO_LEVEL_HIGH,
+	.gpio61 = GPIO_LEVEL_LOW,
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_GPIO,
+	.gpio65 = GPIO_MODE_GPIO,
+	.gpio66 = GPIO_MODE_GPIO,
+	.gpio67 = GPIO_MODE_GPIO,
+	.gpio68 = GPIO_MODE_GPIO,
+	.gpio69 = GPIO_MODE_GPIO,
+	.gpio70 = GPIO_MODE_GPIO,
+	.gpio71 = GPIO_MODE_GPIO,
+	.gpio72 = GPIO_MODE_GPIO,
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio64 = GPIO_DIR_OUTPUT,
+	.gpio65 = GPIO_DIR_OUTPUT,
+	.gpio66 = GPIO_DIR_OUTPUT,
+	.gpio67 = GPIO_DIR_INPUT,
+	.gpio68 = GPIO_DIR_INPUT,
+	.gpio69 = GPIO_DIR_OUTPUT,
+	.gpio70 = GPIO_DIR_OUTPUT,
+	.gpio71 = GPIO_DIR_OUTPUT,
+	.gpio72 = GPIO_DIR_OUTPUT,
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_level = {
+	.gpio64 = GPIO_LEVEL_HIGH,
+	.gpio65 = GPIO_LEVEL_LOW,
+	.gpio66 = GPIO_LEVEL_HIGH,
+	.gpio69 = GPIO_LEVEL_LOW,
+	.gpio70 = GPIO_LEVEL_HIGH,
+	.gpio71 = GPIO_LEVEL_HIGH,
+	.gpio72 = GPIO_LEVEL_HIGH,
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.blink		= &pch_gpio_set1_blink,
+		.invert		= &pch_gpio_set1_invert,
+		.reset		= &pch_gpio_set1_reset,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+		.reset		= &pch_gpio_set2_reset,
+	},
+	.set3 = {
+		.mode		= &pch_gpio_set3_mode,
+		.direction	= &pch_gpio_set3_direction,
+		.level		= &pch_gpio_set3_level,
+		.reset		= &pch_gpio_set3_reset,
+	},
+};
diff --git a/src/mainboard/lenovo/x131e/hda_verb.c b/src/mainboard/lenovo/x131e/hda_verb.c
new file mode 100644
index 0000000000..83b5148278
--- /dev/null
+++ b/src/mainboard/lenovo/x131e/hda_verb.c
@@ -0,0 +1,86 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ * Copyright (C) 2017 James Ye <jye836@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* coreboot specific header */
+	0x10ec0269,	// Codec Vendor / Device ID: Realtek
+	0x17aa21fe,	// Subsystem ID
+	0x0000000b,	// Number of jacks
+
+	/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x17aa21fe */
+	AZALIA_SUBVENDOR(0x0, 0x17aa21fe),
+
+	/* Pin Widget Verb Table */
+
+	/* Pin Complex (NID 0x12): 0x90a60930 DMIC */
+	AZALIA_PIN_CFG(0x0, 0x12, 0x90a60930),
+
+	/* Pin Complex (NID 0x14): 0x90170110 SPEAKER-OUT (Port-D) */
+	AZALIA_PIN_CFG(0x0, 0x14, 0x90170110),
+
+	/* Pin Complex (NID 0x15): 0x0321101f HP-OUT (Port-A) */
+	AZALIA_PIN_CFG(0x0, 0x15, 0x0321101f),
+
+	/* Pin Complex (NID 0x17): 0x411111f0 MONO-OUT (Port-H) */
+	AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0),
+
+	/* Pin Complex (NID 0x18): 0x03a11820 MIC1 (Port-B) */
+	AZALIA_PIN_CFG(0x0, 0x18, 0x03a11820),
+
+	/* Pin Complex (NID 0x19): 0x411111f0 MIC2 (Port-F) */
+	AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0),
+
+	/* Pin Complex (NID 0x1a): 0x411111f0 LINE1 (Port-C) */
+	AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0),
+
+	/* Pin Complex (NID 0x1b): 0x411111f0 LINE2 (Port-E) */
+	AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0),
+
+	/* Pin Complex (NID 0x1d): 0x4016862d PC-BEEP */
+	AZALIA_PIN_CFG(0x0, 0x1d, 0x4016862d),
+
+	/* Pin Complex (NID 0x1e): 0x411111f0 S/PDIF-OUT */
+	AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0),
+
+	/* coreboot specific header */
+	0x80862806,	// Codec Vendor / Device ID: Intel PantherPoint HDMI
+	0x80860101,	// Subsystem ID
+	0x00000004,	// Number of jacks
+
+	/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */
+	AZALIA_SUBVENDOR(0x3, 0x80860101),
+
+	/* Pin Complex (NID 0x05) Digital Out at Int HDMI */
+	AZALIA_PIN_CFG(0x3, 0x05, 0x18560010),
+
+	/* Pin Complex (NID 0x06) Not Connected */
+	AZALIA_PIN_CFG(0x3, 0x06, 0x58560020),
+
+	/* Pin Complex (NID 0x07) Not Connected */
+	AZALIA_PIN_CFG(0x3, 0x07, 0x58560030),
+};
+
+const u32 pc_beep_verbs[] = {
+	0x00170500,	/* power up everything (codec, dac, adc, mixers)  */
+	0x01470740,	/* enable speaker out */
+	0x01470c02,	/* set speaker EAPD pin */
+	0x0143b01f,	/* unmute speaker */
+	0x00c37100,	/* unmute mixer nid 0xc input 1 */
+	0x00b37410,	/* unmute mixer nid 0xb beep input and set volume */
+};
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/lenovo/x131e/mainboard.c b/src/mainboard/lenovo/x131e/mainboard.c
new file mode 100644
index 0000000000..c68b95617a
--- /dev/null
+++ b/src/mainboard/lenovo/x131e/mainboard.c
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 James Ye <jye836@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <ec/lenovo/h8/h8.h>
+
+static void mainboard_enable(device_t dev)
+{
+	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
+					GMA_INT15_PANEL_FIT_DEFAULT,
+					GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+void h8_mainboard_init_dock(void)
+{
+}
+
+struct chip_operations mainboard_ops = {
+	.enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/lenovo/x131e/romstage.c b/src/mainboard/lenovo/x131e/romstage.c
new file mode 100644
index 0000000000..707848b9b3
--- /dev/null
+++ b/src/mainboard/lenovo/x131e/romstage.c
@@ -0,0 +1,70 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ * Copyright (C) 2017 James Ye <jye836@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+void pch_enable_lpc(void)
+{
+	/* EC Decode Range Port60/64, Port62/66 */
+	/* Enable TPM, EC, PS/2 Keyboard/Mouse */
+	pci_write_config16(PCH_LPC_DEV, LPC_EN,
+			   CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
+
+	pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c1611);
+	pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0x00040069);
+	pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, 0x000c0701);
+	pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x000c06a1);
+}
+
+void rcba_config(void)
+{
+	RCBA32(FD) |= PCH_DISABLE_ALWAYS;
+}
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+	{1, 1, 0},
+	{1, 1, 0},
+	{0, 1, 1},
+	{1, 1, 1},
+	{1, 0, 2},
+	{1, 0, 2},
+	{0, 0, 3},
+	{0, 0, 3},
+	{0, 1, 4},
+	{1, 1, 4},
+	{0, 0, 5},
+	{0, 0, 5},
+	{0, 0, 6},
+	{1, 0, 6},
+};
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+	read_spd(&spd[0], 0x50, id_only);
+	read_spd(&spd[2], 0x52, id_only);
+}
+
+void mainboard_early_init(int s3resume)
+{
+}
+
+void mainboard_config_superio(void)
+{
+}
diff --git a/src/mainboard/lenovo/x131e/thermal.h b/src/mainboard/lenovo/x131e/thermal.h
new file mode 100644
index 0000000000..ff928699ae
--- /dev/null
+++ b/src/mainboard/lenovo/x131e/thermal.h
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ * Copyright (C) 2017 James Ye <jye836@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef X131E_THERMAL_H
+#define X131E_THERMAL_H
+
+/* Active Thermal and fans are controlled by the EC. */
+
+/* Temperature which OS will shutdown at */
+#define CRITICAL_TEMPERATURE    100
+
+/* Temperature which OS will throttle CPU */
+#define PASSIVE_TEMPERATURE     90
+
+#endif /* X131E_THERMAL_H */