diff options
author | Felix Held <felix-coreboot@felixheld.de> | 2024-05-17 22:11:09 +0200 |
---|---|---|
committer | Felix Held <felix-coreboot@felixheld.de> | 2024-05-22 15:45:26 +0000 |
commit | be1f05a24f59cbac1dc23b92ec97b3d083d6e077 (patch) | |
tree | 81e3331ddabb1f856d5619f10313a450a40d11b7 /src | |
parent | 27cb75a075c39d43bcaecc95fe05d492fe2f896f (diff) |
mb/amd/birman/devicetree_phoenix_opensil: add static DDI configuration
Add a static DDI port configuration to the devicetree used in the
Phoenix with openSIL case. The configuration is taken from the
birman_ddi_descriptors array in port_descriptor_phoenix.c.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7b85b04114591f3e9da183019c98ca2cb08e59da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82581
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r-- | src/mainboard/amd/birman/devicetree_phoenix_opensil.cb | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb b/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb index bca45598b9..055d9e15e2 100644 --- a/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb +++ b/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb @@ -41,6 +41,32 @@ chip soc/amd/phoenix register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works + register "ddi[0]" = "{ + .connector_type = DDI_EDP, + .aux_index = 0, + .hdp_index = 0, + }" + register "ddi[1]" = "{ + .connector_type = DDI_HDMI, + .aux_index = 1, + .hdp_index = 1, + }" + register "ddi[2]" = "{ + .connector_type = DDI_DP_W_TYPEC, + .aux_index = 2, + .hdp_index = 2, + }" + register "ddi[3]" = "{ + .connector_type = DDI_DP_W_TYPEC, + .aux_index = 3, + .hdp_index = 3, + }" + register "ddi[4]" = "{ + .connector_type = DDI_DP_W_TYPEC, + .aux_index = 4, + .hdp_index = 4, + }" + device domain 0 on device ref iommu on end chip vendorcode/amd/opensil/chip/mpio |