tgl mainboards: Move usb{2,3}_ports settings into XHCI device scope

Change-Id: Ide5126c6e642ca16249efeaf46321724f2ddce9a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>

18 files changed, 210 insertions, 173 deletions

diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
index 8bf1c7dde9..0b3568b646 100644
--- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -90,19 +90,6 @@ chip soc/intel/tigerlake
 	# FSP configuration
 	register "SaGv" = "SaGv_Enabled"
 
-	register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port A0
-	register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port A1
-	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 WWAN
-	register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A / Type-C Cl
-	register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 Camera
-	register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A / Type-C Co
-	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 Bluetooth
-
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)"	# USB3/2 Type A port A0
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)"	# USB3/2 Type A port A1
-	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# M.2 WWAN
-	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# M.2 Camera
-
 	register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC3)"
 	register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC0)"
 
@@ -437,7 +424,24 @@ chip soc/intel/tigerlake
 		end # DPTF				0x9A03
 		device ref gna on end
 		device ref north_xhci on end
-		device ref south_xhci on end
+		device ref south_xhci on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_MID(OC_SKIP),	// Type-A Port A0
+				[1] = USB2_PORT_MID(OC_SKIP),	// Type-A Port A1
+				[2] = USB2_PORT_MID(OC_SKIP),	// M.2 WWAN
+				[3] = USB2_PORT_MID(OC_SKIP),	// Type-A / Type-C Cl
+				[4] = USB2_PORT_MID(OC_SKIP),	// M.2 Camera
+				[8] = USB2_PORT_MID(OC_SKIP),	// Type-A / Type-C Co
+				[9] = USB2_PORT_MID(OC_SKIP),	// M.2 Bluetooth
+			}"
+
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC1),	// USB3/2 Type A port A0
+				[1] = USB3_PORT_DEFAULT(OC2),	// USB3/2 Type A port A1
+				[2] = USB3_PORT_DEFAULT(OC_SKIP),	// M.2 WWAN
+				[3] = USB3_PORT_DEFAULT(OC_SKIP),	// M.2 Camera
+			}"
+		end
 		device ref shared_ram on end
 		device ref cnvi_wifi on
 			chip drivers/wifi/generic
diff --git a/src/mainboard/google/volteer/variants/chronicler/overridetree.cb b/src/mainboard/google/volteer/variants/chronicler/overridetree.cb
index 53ed651bdd..fc5d6ab063 100644
--- a/src/mainboard/google/volteer/variants/chronicler/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/chronicler/overridetree.cb
@@ -66,15 +66,6 @@ chip soc/intel/tigerlake
 		},
 	}"
 
-	# Disable M.2 WWAN
-	register "usb2_ports[2]" = "USB2_PORT_EMPTY"
-
-	# Type-A / Type-C C1
-	register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)"
-
-	# Type-A / Type-C C0
-	register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)"
-
 	device domain 0 on
 		device ref dptf on
 			chip drivers/intel/dptf
@@ -146,6 +137,12 @@ chip soc/intel/tigerlake
 			end
 		end
 		device ref south_xhci on
+			register "usb2_ports" = "{
+				[2] = USB2_PORT_EMPTY,			// Disable M.2 WWAN
+				[3] = USB2_PORT_TYPE_C(OC_SKIP),	// Type-A / Type-C C1
+				[8] = USB2_PORT_TYPE_C(OC_SKIP),	// Type-A / Type-C C0
+			}"
+
 			chip drivers/usb/acpi
 				device ref xhci_root_hub on
 					chip drivers/usb/acpi
diff --git a/src/mainboard/google/volteer/variants/collis/overridetree.cb b/src/mainboard/google/volteer/variants/collis/overridetree.cb
index a50274f66f..ab4137e590 100644
--- a/src/mainboard/google/volteer/variants/collis/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/collis/overridetree.cb
@@ -15,15 +15,6 @@ chip soc/intel/tigerlake
 	register "DdiPort1Hpd" = "0"
 	register "DdiPort2Hpd" = "0"
 
-	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC1)"	# Type-A Port A0
-	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)"	# Type-A Port A1
-	register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC0)"	# Type-C Port C1
-	register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"	# Front Camera
-	register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC3)"	# Type-C Port C0
-	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"	# WFC Camera
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)"	# USB3/2 Type-A Port A0
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)"	# USB3/2 Type-A Port A1
-
 	# Disable SRCCLKREQ1#
 	register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED"
 
@@ -248,6 +239,20 @@ chip soc/intel/tigerlake
 			end
 		end
 		device ref south_xhci on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_TYPE_C(OC1),	// Type-A Port A0
+				[1] = USB2_PORT_TYPE_C(OC2),	// Type-A Port A1
+				[2] = USB2_PORT_TYPE_C(OC0),	// Type-C Port C1
+				[3] = USB2_PORT_MID(OC_SKIP),	// Front Camera
+				[4] = USB2_PORT_TYPE_C(OC3),	// Type-C Port C0
+				[5] = USB2_PORT_MID(OC_SKIP),	// WFC Camera
+			}"
+
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC1),	// USB3/2 Type-A Port A0
+				[1] = USB3_PORT_DEFAULT(OC2),	// USB3/2 Type-A Port A1
+			}"
+
 			chip drivers/usb/acpi
 				device ref xhci_root_hub on
 					chip drivers/usb/acpi
diff --git a/src/mainboard/google/volteer/variants/copano/overridetree.cb b/src/mainboard/google/volteer/variants/copano/overridetree.cb
index 87abc9bd91..619b203f9f 100644
--- a/src/mainboard/google/volteer/variants/copano/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/copano/overridetree.cb
@@ -12,13 +12,6 @@ chip soc/intel/tigerlake
 	# and controller 1 channel 0 and 1.
 	register "CmdMirror" = "0x00000033"
 
-	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"	# Type-A / Type-C Port 0
-	register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC1)"	# Type-A / Type-C Port 1
-	register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"	# Front Camera
-	register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC0)"	# Type-A / Type-C Port 0
-
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"	# Type-A / Type-C Port 0
-
 	# Disable SRCCLKREQ1#
 	register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED"
 
@@ -273,6 +266,15 @@ chip soc/intel/tigerlake
 			end
 		end
 		device ref south_xhci on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_TYPE_C(OC0),	// Type-A / Type-C Port 0
+				[2] = USB2_PORT_TYPE_C(OC1),	// Type-A / Type-C Port 1
+				[3] = USB2_PORT_MID(OC_SKIP),	// Front Camera
+				[4] = USB2_PORT_TYPE_C(OC0),	// Type-A / Type-C Port 0
+			}"
+
+			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"	# Type-A / Type-C Port 0
+
 			chip drivers/usb/acpi
 				device ref xhci_root_hub on
 					chip drivers/usb/acpi
diff --git a/src/mainboard/google/volteer/variants/delbin/overridetree.cb b/src/mainboard/google/volteer/variants/delbin/overridetree.cb
index cc970f7f1d..c4f915c12e 100644
--- a/src/mainboard/google/volteer/variants/delbin/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/delbin/overridetree.cb
@@ -51,16 +51,6 @@ chip soc/intel/tigerlake
 			},
 		},
 	}"
-	#These settings improve the USB2 Port1 eye diagram
-	register "usb2_ports[3]" = "{
-		.enable = 1,
-		.tx_bias = USB2_BIAS_28P15MV,
-		.tx_emp_enable = USB2_PRE_EMP_ON,
-		.pre_emp_bias = USB2_BIAS_56P3MV,
-		.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
-		.type_c = 1,
-	}"
-	register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)"
 
 	register "tcc_offset" = "8"
 
@@ -255,6 +245,20 @@ chip soc/intel/tigerlake
 			end
 		end
 		device ref south_xhci on
+			register "usb2_ports" = "{
+				// These settings improve the USB2 Port4 eye diagram
+				[3] = {
+					.enable = 1,
+					.tx_bias = USB2_BIAS_28P15MV,
+					.tx_emp_enable = USB2_PRE_EMP_ON,
+					.pre_emp_bias = USB2_BIAS_56P3MV,
+					.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
+					.type_c = 1,
+				},
+				[8] = USB2_PORT_TYPE_C(OC_SKIP),
+			}"
+
+
 			chip drivers/usb/acpi
 				device ref xhci_root_hub on
 					chip drivers/usb/acpi
diff --git a/src/mainboard/google/volteer/variants/drobit/overridetree.cb b/src/mainboard/google/volteer/variants/drobit/overridetree.cb
index e8bb664cab..aefe14186a 100644
--- a/src/mainboard/google/volteer/variants/drobit/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/drobit/overridetree.cb
@@ -17,9 +17,6 @@ chip soc/intel/tigerlake
 		.tdp_pl4 = 105,
 	}"
 
-	register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC0)"     # Type-C port 1
-	register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC3)"     # Type-C port 0
-
 	#+-------------------+---------------------------+
 	#| Field             |  Value                    |
 	#+-------------------+---------------------------+
@@ -260,6 +257,11 @@ chip soc/intel/tigerlake
 			end
 		end
 		device ref south_xhci on
+			register "usb2_ports" = "{
+				[3] = USB2_PORT_TYPE_C(OC0),	// Type-C port 1
+				[8] = USB2_PORT_TYPE_C(OC3),	// Type-C port 0
+			}"
+
 			chip drivers/usb/acpi
 				device ref xhci_root_hub on
 					chip drivers/usb/acpi
diff --git a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb
index 7bb91eacef..2b2f32c5ac 100644
--- a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb
@@ -59,36 +59,6 @@ chip soc/intel/tigerlake
 		},
 	}"
 
-	#Disable Type-A Port A1
-	register "usb2_ports[1]" = "USB2_PORT_EMPTY"
-
-	#Disable M.2 WWAN
-	register "usb2_ports[2]" = "USB2_PORT_EMPTY"
-
-	#improve the USB2 Port1 eye diagram
-	register "usb2_ports[3]" = "{
-		.enable = 1,
-		.ocpin = OC_SKIP,
-		.tx_bias = USB2_BIAS_39P35MV,
-		.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON,
-		.pre_emp_bias = USB2_BIAS_39P35MV,
-		.pre_emp_bit = USB2_FULL_BIT_PRE_EMP,
-		.type_c = 1,
-	}"
-
-	#lower camera driving
-	register "usb2_ports[4]" = "{
-		.enable = 1,
-		.ocpin = OC_SKIP,
-		.tx_bias = USB2_BIAS_0MV,
-		.tx_emp_enable = USB2_EMP_OFF,
-		.pre_emp_bias = USB2_BIAS_0MV,
-		.pre_emp_bit = USB2_FULL_BIT_PRE_EMP,
-	}"
-
-	#Type-A / Type-C C0
-	register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)"
-
 	device domain 0 on
 		device ref dptf on
 			# DPTF Policy for Eldrid board
@@ -252,6 +222,35 @@ chip soc/intel/tigerlake
 			end
 		end
 		device ref south_xhci on
+			register "usb2_ports" = "{
+				[1] = USB2_PORT_EMPTY,	// Disable Type-A Port A1
+				[2] = USB2_PORT_EMPTY,	// Disable M.2 WWAN
+
+				// improve the USB2 Port1 eye diagram
+				[3] = {
+					.enable = 1,
+					.ocpin = OC_SKIP,
+					.tx_bias = USB2_BIAS_39P35MV,
+					.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON,
+					.pre_emp_bias = USB2_BIAS_39P35MV,
+					.pre_emp_bit = USB2_FULL_BIT_PRE_EMP,
+					.type_c = 1,
+				},
+
+				// lower camera driving
+				[4] = {
+					.enable = 1,
+					.ocpin = OC_SKIP,
+					.tx_bias = USB2_BIAS_0MV,
+					.tx_emp_enable = USB2_EMP_OFF,
+					.pre_emp_bias = USB2_BIAS_0MV,
+					.pre_emp_bit = USB2_FULL_BIT_PRE_EMP,
+				},
+
+				// Type-A / Type-C C0
+				[8] = USB2_PORT_TYPE_C(OC_SKIP),
+			}"
+
 			chip drivers/usb/acpi
 				device ref xhci_root_hub on
 					chip drivers/usb/acpi
diff --git a/src/mainboard/google/volteer/variants/elemi/overridetree.cb b/src/mainboard/google/volteer/variants/elemi/overridetree.cb
index 4adf76a882..5eef9ef177 100644
--- a/src/mainboard/google/volteer/variants/elemi/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/elemi/overridetree.cb
@@ -66,15 +66,6 @@ chip soc/intel/tigerlake
 		},
 	}"
 
-	# Disable M.2 WWAN
-	register "usb2_ports[2]" = "USB2_PORT_EMPTY"
-
-	# Type-A / Type-C C1
-	register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)"
-
-	# Type-A / Type-C C0
-	register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)"
-
 	device domain 0 on
 		device ref dptf on
 			chip drivers/intel/dptf
@@ -146,6 +137,12 @@ chip soc/intel/tigerlake
 			end
 		end
 		device ref south_xhci on
+			register "usb2_ports" = "{
+				[2] = USB2_PORT_EMPTY,			// Disable M.2 WWAN
+				[3] = USB2_PORT_TYPE_C(OC_SKIP),	// Type-A / Type-C C1
+				[8] = USB2_PORT_TYPE_C(OC_SKIP),	// Type-A / Type-C C0
+			}"
+
 			chip drivers/usb/acpi
 				device ref xhci_root_hub on
 					chip drivers/usb/acpi
diff --git a/src/mainboard/google/volteer/variants/halvor/overridetree.cb b/src/mainboard/google/volteer/variants/halvor/overridetree.cb
index 138d55796d..589dfaf25a 100644
--- a/src/mainboard/google/volteer/variants/halvor/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/halvor/overridetree.cb
@@ -1,10 +1,4 @@
 chip soc/intel/tigerlake
-	register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A / Type-C Port 0
-	register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A / Type-C Port 1
-	register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)"	# Front Camera
-	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A / Type-C Port 2
-	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# Reserve for CNVi BT
-
 	register "SaGv" = "SaGv_Disabled"
 
 	device domain 0 on
@@ -128,6 +122,14 @@ chip soc/intel/tigerlake
 			end
 		end
 		device ref south_xhci on
+			register "usb2_ports" = "{
+				[1] = USB2_PORT_MID(OC_SKIP),	// Type-A / Type-C Port 0
+				[3] = USB2_PORT_MID(OC_SKIP),	// Type-A / Type-C Port 1
+				[4] = USB2_PORT_MID(OC_SKIP),	// Front Camera
+				[5] = USB2_PORT_MID(OC_SKIP),	// Type-A / Type-C Port 2
+				[9] = USB2_PORT_MID(OC_SKIP),	// Reserve for CNVi BT
+			}"
+
 			chip drivers/usb/acpi
 				device ref xhci_root_hub on
 					chip drivers/usb/acpi
diff --git a/src/mainboard/google/volteer/variants/lindar/overridetree.cb b/src/mainboard/google/volteer/variants/lindar/overridetree.cb
index b74bb238cd..2229af7d1d 100644
--- a/src/mainboard/google/volteer/variants/lindar/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/lindar/overridetree.cb
@@ -4,15 +4,6 @@ chip soc/intel/tigerlake
 	register "TcssAuxOri" = "1"
 	register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E10, .pad_auxn_dc = GPP_E13}"
 
-	# USB Port Config
-	register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port A0
-	register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# Type-A / Type-C C1
-	register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 Camera
-	register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# Type-A / Type-C C0
-	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 Bluetooth
-
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)"	# USB3/2 Type A port A0
-
 	#+-------------------+---------------------------+
 	#| Field             |  Value                    |
 	#+-------------------+---------------------------+
@@ -327,6 +318,16 @@ chip soc/intel/tigerlake
 			end
 		end
 		device ref south_xhci on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_MID(OC_SKIP),		// Type-A Port A0
+				[3] = USB2_PORT_TYPE_C(OC_SKIP),	// Type-A / Type-C C1
+				[4] = USB2_PORT_MID(OC_SKIP),		// M.2 Camera
+				[8] = USB2_PORT_TYPE_C(OC_SKIP),	// Type-A / Type-C C0
+				[9] = USB2_PORT_MID(OC_SKIP),		// M.2 Bluetooth
+			}"
+
+			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)"	# USB3/2 Type A port A0
+
 			chip drivers/usb/acpi
 				device ref xhci_root_hub on
 					chip drivers/usb/acpi
diff --git a/src/mainboard/google/volteer/variants/malefor/overridetree.cb b/src/mainboard/google/volteer/variants/malefor/overridetree.cb
index 62d81906ba..1942657858 100644
--- a/src/mainboard/google/volteer/variants/malefor/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/malefor/overridetree.cb
@@ -1,14 +1,5 @@
 chip soc/intel/tigerlake
 
-	# USB Port Config
-	register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port A0
-	register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A / Type-C C1
-	register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 Camera
-	register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A / Type-C C0
-	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 Bluetooth
-
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)"	# USB3/2 Type A port A0
-
 	register "SaGv" = "SaGv_Disabled"
 
 	register "TcssAuxOri" = "1"
@@ -113,6 +104,16 @@ chip soc/intel/tigerlake
 			end
 		end
 		device ref south_xhci on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_MID(OC_SKIP),	// Type-A Port A0
+				[3] = USB2_PORT_MID(OC_SKIP),	// Type-A / Type-C C1
+				[4] = USB2_PORT_MID(OC_SKIP),	// M.2 Camera
+				[8] = USB2_PORT_MID(OC_SKIP),	// Type-A / Type-C C0
+				[9] = USB2_PORT_MID(OC_SKIP),	// M.2 Bluetooth
+			}"
+
+			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)"	# USB3/2 Type A port A0
+
 			chip drivers/usb/acpi
 				device ref xhci_root_hub on
 					chip drivers/usb/acpi
diff --git a/src/mainboard/google/volteer/variants/terrador/overridetree.cb b/src/mainboard/google/volteer/variants/terrador/overridetree.cb
index 4113db7de6..4b814ebf2d 100644
--- a/src/mainboard/google/volteer/variants/terrador/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/terrador/overridetree.cb
@@ -5,15 +5,6 @@ chip soc/intel/tigerlake
 	# and controller 1 channel 0 and 1.
 	register "CmdMirror" = "0x00000033"
 
-	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"	# Type-A / Type-C Port 0
-	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)"	# Type-A / Type-C Port 1
-	register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC1)"	# Type-A / Type-C Port 1
-	register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"	# Front Camera
-	register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC0)"	# Type-A / Type-C Port 0
-
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"	# Type-A / Type-C Port 0
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)"	# Type-A / Type-C Port 1
-
 	# Disable SRCCLKREQ1#
 	register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED"
 
@@ -195,6 +186,19 @@ chip soc/intel/tigerlake
 			end
 		end
 		device ref south_xhci on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_TYPE_C(OC0),	// Type-A / Type-C Port 0
+				[1] = USB2_PORT_TYPE_C(OC1),	// Type-A / Type-C Port 1
+				[2] = USB2_PORT_TYPE_C(OC1),	// Type-A / Type-C Port 1
+				[3] = USB2_PORT_MID(OC_SKIP),	// Front Camera
+				[4] = USB2_PORT_TYPE_C(OC0),	// Type-A / Type-C Port 0
+			}"
+
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC0),	// Type-A / Type-C Port 0
+				[1] = USB3_PORT_DEFAULT(OC1),	// Type-A / Type-C Port 1
+			}"
+
 			chip drivers/usb/acpi
 				device ref xhci_root_hub on
 					chip drivers/usb/acpi
diff --git a/src/mainboard/google/volteer/variants/todor/overridetree.cb b/src/mainboard/google/volteer/variants/todor/overridetree.cb
index f500e9aa76..c511fed556 100644
--- a/src/mainboard/google/volteer/variants/todor/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/todor/overridetree.cb
@@ -5,21 +5,26 @@ chip soc/intel/tigerlake
 	# and controller 1 channel 0 and 1.
 	register "CmdMirror" = "0x00000033"
 
-	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"	# Type-A / Type-C Port 0
-	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)"	# Type-A / Type-C Port 1
-	register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC1)"	# Type-A / Type-C Port 1
-	register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"	# Front Camera
-	register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC0)"	# Type-A / Type-C Port 0
-
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"	# Type-A / Type-C Port 0
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)"	# Type-A / Type-C Port 1
-
 	register "SaGv" = "SaGv_Disabled"
 
 	# Disable SRCCLKREQ1#
 	register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED"
 
 	device domain 0 on
+		device ref south_xhci on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_TYPE_C(OC0),	// Type-A / Type-C Port 0
+				[1] = USB2_PORT_TYPE_C(OC1),	// Type-A / Type-C Port 1
+				[2] = USB2_PORT_TYPE_C(OC1),	// Type-A / Type-C Port 1
+				[3] = USB2_PORT_MID(OC_SKIP),	// Front Camera
+				[4] = USB2_PORT_TYPE_C(OC0),	// Type-A / Type-C Port 0
+			}"
+
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC0),	// Type-A / Type-C Port 0
+				[1] = USB3_PORT_DEFAULT(OC1),	// Type-A / Type-C Port 1
+			}"
+		end
 		device ref dptf on
 			chip drivers/intel/dptf
 				## Disable Active Policy
diff --git a/src/mainboard/google/volteer/variants/voema/overridetree.cb b/src/mainboard/google/volteer/variants/voema/overridetree.cb
index 4c83c7e42d..97160ee269 100644
--- a/src/mainboard/google/volteer/variants/voema/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/voema/overridetree.cb
@@ -5,9 +5,6 @@ chip soc/intel/tigerlake
 	# and controller 1 channel 0 and 1.
 	register "CmdMirror" = "0x00000033"
 
-	register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# Type-A / Type-C Port 1
-	register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# Type-A / Type-C Port 0
-
 	register "TcssAuxOri" = "1"
 	register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E10, .pad_auxn_dc = GPP_E13}"
 
@@ -159,6 +156,11 @@ chip soc/intel/tigerlake
 			end
 		end
 		device ref south_xhci on
+			register "usb2_ports" = "{
+				[2] = USB2_PORT_TYPE_C(OC_SKIP),	// Type-A / Type-C Port 1
+				[4] = USB2_PORT_TYPE_C(OC_SKIP),	// Type-A / Type-C Port 0
+			}"
+
 			chip drivers/usb/acpi
 				device ref xhci_root_hub on
 					chip drivers/usb/acpi
diff --git a/src/mainboard/google/volteer/variants/volet/overridetree.cb b/src/mainboard/google/volteer/variants/volet/overridetree.cb
index 52a198e10f..7125f40578 100644
--- a/src/mainboard/google/volteer/variants/volet/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/volet/overridetree.cb
@@ -2,9 +2,6 @@ chip soc/intel/tigerlake
 	register "DdiPort1Hpd" = "0"
 	register "DdiPort2Hpd" = "0"
 
-	register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)"     # Type-A / Type-C Cl
-	register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)"     # Type-A / Type-C C0
-
 	register "TcssAuxOri" = "1"
 	register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E10, .pad_auxn_dc = GPP_E13}"
 
@@ -185,6 +182,11 @@ chip soc/intel/tigerlake
 			end
 		end
 		device ref south_xhci on
+			register "usb2_ports" = "{
+				[3] = USB2_PORT_TYPE_C(OC_SKIP),	// Type-A / Type-C Cl
+				[8] = USB2_PORT_TYPE_C(OC_SKIP),	// Type-A / Type-C C0
+			}"
+
 			chip drivers/usb/acpi
 				device ref xhci_root_hub on
 					chip drivers/usb/acpi
diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb
index b517ba274e..836753349c 100644
--- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb
@@ -13,9 +13,6 @@ chip soc/intel/tigerlake
 		.tdp_pl4 = 105,
 	}"
 
-	register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)"     # Type-A / Type-C Cl
-	register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)"     # Type-A / Type-C C0
-
 	# Disable SRCCLKREQ1#
 	register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED"
 
@@ -280,6 +277,11 @@ chip soc/intel/tigerlake
 			end
 		end
 		device ref south_xhci on
+			register "usb2_ports" = "{
+				[3] = USB2_PORT_TYPE_C(OC_SKIP),	// Type-A / Type-C Cl
+				[8] = USB2_PORT_TYPE_C(OC_SKIP),	// Type-A / Type-C C0
+			}"
+
 			chip drivers/usb/acpi
 				device ref xhci_root_hub on
 					chip drivers/usb/acpi
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index ecad52e60a..1bce4b20a8 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -14,20 +14,6 @@ chip soc/intel/tigerlake
 	# CNVi BT enable/disable
 	register "CnviBtCore" = "true"
 
-	register "usb2_ports[0]" = "USB2_PORT_MID(OC0)"		# Type-C Port1
-	register "usb2_ports[1]" = "USB2_PORT_EMPTY"		# M.2 WWAN
-	register "usb2_ports[2]" = "USB2_PORT_MID(OC3)"		# M.2 Bluetooth
-	register "usb2_ports[3]" = "USB2_PORT_MID(OC0)"		# USB3/2 Type A port1
-	register "usb2_ports[4]" = "USB2_PORT_MID(OC0)"		# Type-C Port2
-	register "usb2_ports[5]" = "USB2_PORT_MID(OC3)"		# Type-C Port3
-	register "usb2_ports[6]" = "USB2_PORT_MID(OC3)"		# Type-C Port4
-	register "usb2_ports[7]" = "USB2_PORT_MID(OC0)"		# USB3/2 Type A port2
-	register "usb2_ports[8]" = "USB2_PORT_MID(OC3)"		# USB2 Type A port3
-	register "usb2_ports[9]" = "USB2_PORT_MID(OC3)"		# USB2 Type A port4
-
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"	# USB3/2 Type A port1
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"	# USB3/2 Type A port2
-
 	# CPU replacement check
 	register "CpuReplacementCheck" = "1"
 
@@ -206,7 +192,25 @@ chip soc/intel/tigerlake
 		end
 		device ref gspi2 off end
 		device ref gspi3 off end
-		device ref south_xhci on  end
+		device ref south_xhci on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_MID(OC0),	// Type-C Port1
+				[1] = USB2_PORT_EMPTY,		// M.2 WWAN
+				[2] = USB2_PORT_MID(OC3),	// M.2 Bluetooth
+				[3] = USB2_PORT_MID(OC0),	// USB3/2 Type A port1
+				[4] = USB2_PORT_MID(OC0),	// Type-C Port2
+				[5] = USB2_PORT_MID(OC3),	// Type-C Port3
+				[6] = USB2_PORT_MID(OC3),	// Type-C Port4
+				[7] = USB2_PORT_MID(OC0),	// USB3/2 Type A port2
+				[8] = USB2_PORT_MID(OC3),	// USB2 Type A port3
+				[9] = USB2_PORT_MID(OC3),	// USB2 Type A port4
+			}"
+
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC0),	// USB3/2 Type A port1
+				[1] = USB3_PORT_DEFAULT(OC0),	// USB3/2 Type A port2
+			}"
+		end
 		device ref south_xdci on  end
 		device ref shared_ram on  end
 		device ref cnvi_wifi on
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
index 4a523a7a1a..7a310988a8 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
@@ -14,21 +14,6 @@ chip soc/intel/tigerlake
 	# CNVi BT enable/disable
 	register "CnviBtCore" = "true"
 
-	register "usb2_ports[0]" = "USB2_PORT_MID(OC3)"		# Type-C Port1
-	register "usb2_ports[1]" = "USB2_PORT_EMPTY"		# M.2 WWAN
-	register "usb2_ports[2]" = "USB2_PORT_MID(OC0)"		# M.2 Bluetooth, USB3/2 Type A Port1
-	register "usb2_ports[3]" = "USB2_PORT_MID(OC3)"		# USB3/2 Type A Port 1
-	register "usb2_ports[4]" = "USB2_PORT_MID(OC3)"		# Type-C Port2
-	register "usb2_ports[5]" = "USB2_PORT_MID(OC3)"		# Type-C Port3 / MECC
-	register "usb2_ports[6]" = "USB2_PORT_EMPTY"		# Not used
-	register "usb2_ports[7]" = "USB2_PORT_EMPTY"		# Not used
-	register "usb2_ports[8]" = "USB2_PORT_EMPTY"		# Not used
-	register "usb2_ports[9]" = "USB2_PORT_MID(OC3)"		# CNVi/BT
-
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"	# USB3/2 Type A port1
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"	# USB3/2 Type A port2
-	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)"	# USB3/USB2 Flex Connector
-
 	# CPU replacement check
 	register "CpuReplacementCheck" = "1"
 
@@ -215,7 +200,26 @@ chip soc/intel/tigerlake
 		end
 		device ref gspi2 off end
 		device ref gspi3 off end
-		device ref south_xhci on  end
+		device ref south_xhci on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_MID(OC3),	// Type-C Port1
+				[1] = USB2_PORT_EMPTY,		// M.2 WWAN
+				[2] = USB2_PORT_MID(OC0),	// M.2 Bluetooth, USB3/2 Type A Port1
+				[3] = USB2_PORT_MID(OC3),	// USB3/2 Type A Port 1
+				[4] = USB2_PORT_MID(OC3),	// Type-C Port2
+				[5] = USB2_PORT_MID(OC3),	// Type-C Port3 / MECC
+				[6] = USB2_PORT_EMPTY,		// Not used
+				[7] = USB2_PORT_EMPTY,		// Not used
+				[8] = USB2_PORT_EMPTY,		// Not used
+				[9] = USB2_PORT_MID(OC3),	// CNVi/BT
+			}"
+
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC0),	// USB3/2 Type A port1
+				[1] = USB3_PORT_DEFAULT(OC0),	// USB3/2 Type A port2
+				[3] = USB3_PORT_DEFAULT(OC3),	// USB3/USB2 Flex Connector
+			}"
+		end
 		device ref south_xdci on  end
 		device ref shared_ram on  end
 		device ref cnvi_wifi on