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authorMorris Hsu <morris-hsu@quanta.corp-partner.google.com>2023-03-31 14:53:02 +0800
committerFelix Held <felix-coreboot@felixheld.de>2023-04-03 13:24:55 +0000
commitb99cd85f740e15688578ab16dd5156d5709baef0 (patch)
treee776f64625ef6cd7a20ab1693af6213b807dbe22 /src
parent0973c32c5db020df873dc531ba214737ea7e7599 (diff)
mb/google/brask/var/constitution: correct Type-A USB3 port0/1 tx_de_emp
Set Type-A USB3 port0/1 tx_de_emp to 0x2B to fix the USB3 Gen2 RX signal integrity issue. BUG=None TEST=build FW and check Type-A USB3 port0/port1 RX pass Change-Id: I9296ae5a8a9d7aa49b3c7529a9c1b2d2829b15d0 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/brya/variants/constitution/overridetree.cb13
1 files changed, 13 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/constitution/overridetree.cb b/src/mainboard/google/brya/variants/constitution/overridetree.cb
index 67684b9891..4b894b02f8 100644
--- a/src/mainboard/google/brya/variants/constitution/overridetree.cb
+++ b/src/mainboard/google/brya/variants/constitution/overridetree.cb
@@ -22,6 +22,19 @@ chip soc/intel/alderlake
register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Disable USB2 Port 5
register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2 Port 6
+ register "usb3_ports[0]" = "{
+ .enable = 1,
+ .ocpin = OC_SKIP,
+ .tx_de_emp = 0x2B,
+ .tx_downscale_amp = 0x00,
+ }" # Type-A port A0
+ register "usb3_ports[1]" = "{
+ .enable = 1,
+ .ocpin = OC_SKIP,
+ .tx_de_emp = 0x2B,
+ .tx_downscale_amp = 0x00,
+ }" # Type-A port A1
+
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # HDMI-IN
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Disable Type-A port A3