urara: Identity map DRAM/SRAM

Using identity_map(), map the DRAM/SRAM regions to themselves (which
happens to be using KUSEG on urara).

The bootblock (which still runs in KSEG0) sets up the identity mapping
in bootblock_mmu_init() so that ROM/RAM stages can be loaded into the
KUSEG address range.

The stack and pre-RAM CBMEM console also remain in KSEG0 since we
don't really care about their physical addresses.

Also splitting CBFS cache to pre and post RAM, to allow for larger
rambase images.

BUG=chrome-os-partner:36258
BRANCH=none
TEST=With the rest of coreboot and depthcharge patches applied:
    - booted urara into the kernel login prompt
    - from depthcharge CLI tried accessing memory below 0x100000 -
      observed the exception.

Change-Id: If78f1c5c54d3587fe83e25c79698b2e9e41d3309
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9668b440b35805e8ce442be62f67053cedcb205e
Original-Change-Id: I187d02fa2ace08b9fb7a333c928e92c54465abc2
Original-Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/246694
Reviewed-on: http://review.coreboot.org/9816
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

3 files changed, 51 insertions, 11 deletions

diff --git a/src/arch/mips/bootblock_simple.c b/src/arch/mips/bootblock_simple.c
index 747a8bfff6..64bbae23a4 100644
--- a/src/arch/mips/bootblock_simple.c
+++ b/src/arch/mips/bootblock_simple.c
@@ -32,5 +32,7 @@ void main(void)
 	console_init();
 #endif
 
+	bootblock_mmu_init();
+
 	run_romstage();
 }
diff --git a/src/soc/imgtec/pistachio/bootblock.c b/src/soc/imgtec/pistachio/bootblock.c
index 90112646c4..1276a24153 100644
--- a/src/soc/imgtec/pistachio/bootblock.c
+++ b/src/soc/imgtec/pistachio/bootblock.c
@@ -21,6 +21,9 @@
 
 #include <stdint.h>
 #include <arch/cpu.h>
+#include <arch/mmu.h>
+#include <assert.h>
+#include <symbols.h>
 
 static void bootblock_cpu_init(void)
 {
@@ -37,3 +40,26 @@ static void bootblock_cpu_init(void)
 	/* And make sure that it starts from zero. */
 	write_c0_count(0);
 }
+
+static void bootblock_mmu_init(void)
+{
+	uint32_t null_guard_size =  1 * MiB;
+	uint32_t dram_base, dram_size;
+
+	write_c0_wired(0);
+
+	dram_base = (uint32_t)_dram;
+	dram_size = CONFIG_DRAM_SIZE_MB * MiB;
+
+	/*
+	 * To be able to catch NULL pointer dereference attempts, lets not map
+	 * memory close to zero.
+	 */
+	if (dram_base < null_guard_size) {
+		dram_base += null_guard_size;
+		dram_size -= null_guard_size;
+	}
+
+	assert(!identity_map(dram_base, dram_size));
+	assert(!identity_map((uint32_t)_sram, _sram_size));
+}
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index 5b50a0a365..802592f4d5 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -23,20 +23,32 @@
 
 SECTIONS
 {
-	DRAM_START(0x80000000)
-	RAMSTAGE(0x80000000, 128K)
+	/*
+	 * All of DRAM (other than the DMA coherent area) is accessed through
+	 * the identity mapping.
+	 */
+	DRAM_START(0x00000000)
+	/* DMA coherent area: accessed via KSEG1. */
+	DMA_COHERENT(0x00100000, 1M)
+	POSTRAM_CBFS_CACHE(0x00200000, 128K)
+	RAMSTAGE(0x00220000, 128K)
 
-	/* GRAM becomes the SRAM. */
-	SRAM_START(0x9a000000)
+	/*
+	 * GRAM becomes the SRAM.  Accessed through KSEG0 in the bootblock
+	 * and then through the identity mapping in ROM stage.
+	 */
+	SRAM_START(0x1a000000)
+	ROMSTAGE(0x1a004800, 36K)
+	PRERAM_CBFS_CACHE(0x1a00d800, 74K)
+	SRAM_END(0x1a020000)
+
+	/* Bootblock executes out of KSEG0 and sets up the identity mapping. */
 	BOOTBLOCK(0x9a000000, 18K)
-	ROMSTAGE(0x9a004800, 36K)
-	CBFS_CACHE(0x9a00d800, 74K)
-	SRAM_END(0x9a020000)
 
-	/* Let's use SRAM for stack and CBMEM console. */
+	/*
+	 * Let's use SRAM for stack and CBMEM console.  Always accessed
+	 * through KSEG0.
+	 */
 	STACK(0x9b000000, 8K)
 	PRERAM_CBMEM_CONSOLE(0x9b002000, 8K)
-
-	/* DMA coherent area: end of available DRAM, uncached */
-	DMA_COHERENT(0xAFF00000, 1M)
 }