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authorRichard Spiegel <richard.spiegel@amd.corp-partner.google.com>2018-08-20 13:52:44 -0700
committerMartin Roth <martinroth@google.com>2018-08-22 15:36:10 +0000
commitb74e399c7d9d6decd6aeba5de5a8181a5f17d82a (patch)
tree6e98eabed6bcc6ae886ba51ee133181c6dc3146a /src
parente6809907e7ea2dcecb8f94222dfde9f2d52de688 (diff)
soc/amd/stoneyridge/smihandler.c: Report pending wake event
There's a small window of opportunity when CPU is already in SMM but has not yet entered S3 for a wake event to happen, which would cause a failed S3 entry. Check for pending events at the very last moment possible, and if there are pending wake events report them. BUG=b:111100312 TEST=build and boot grunt. Change-Id: I9472fdf481897fcf9f4c669f6b1514ef479fce7a Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/amd/stoneyridge/smihandler.c26
1 files changed, 25 insertions, 1 deletions
diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c
index ef24baaac4..eeedba70d2 100644
--- a/src/soc/amd/stoneyridge/smihandler.c
+++ b/src/soc/amd/stoneyridge/smihandler.c
@@ -122,7 +122,8 @@ static void disable_all_smi_status(void)
static void sb_slp_typ_handler(void)
{
- uint32_t pm1cnt, pci_ctrl;
+ uint32_t pm1cnt, pci_ctrl, reg32;
+ uint16_t reg16;
uint8_t slp_typ, rst_ctrl;
/* Figure out SLP_TYP */
@@ -171,6 +172,29 @@ static void sb_slp_typ_handler(void)
rst_ctrl |= SLPTYPE_CONTROL_EN;
pm_write8(PM_RST_CTRL1, rst_ctrl);
+ /*
+ * Before the final command, check if there's pending wake
+ * event. Read enable first, so that reading the actual status
+ * is as close as possible to entering S3. The idea is to
+ * minimize the opportunity for a wake event to happen before
+ * actually entering S3. If there's a pending wake event, log
+ * it and continue normal path. S3 will fail and the wake event
+ * becomes a SCI.
+ */
+ if (IS_ENABLED(CONFIG_ELOG_GSMI)) {
+ reg16 = inw(ACPI_PM1_EN) & inw(ACPI_PM1_STS);
+ if (reg16)
+ elog_add_extended_event(
+ ELOG_SLEEP_PENDING_PM1_WAKE,
+ (u32)reg16);
+
+ reg32 = inl(ACPI_GPE0_EN) & inl(ACPI_GPE0_STS);
+ if (reg32)
+ elog_add_extended_event(
+ ELOG_SLEEP_PENDING_GPE0_WAKE,
+ reg32);
+ } /* if (IS_ENABLED(CONFIG_ELOG_GSMI)) */
+
/* Reissue Pm1 write */
outl(pm1cnt | SLP_EN, pm_acpi_pm_cnt_blk());
hlt();