diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2022-08-08 21:27:32 +0200 |
|---|---|---|
| committer | Martin Roth <martin.roth@amd.corp-partner.google.com> | 2022-08-13 19:28:24 +0000 |
| commit | b65845cb2b0009d1ed1e9b8550cbcd4c1d093c63 (patch) | |
| tree | caefdeffdd190b8bbd02fb6838a54995168fcb38 /src | |
| parent | 5e0cd9fd4bba28ac3d07c17a0d1bee5cdeaf19f2 (diff) | |
vc/amd/fsp/cezanne,mendocino: add FSP CCX CPPC HOB GUID and struct
To generate a complete _CPC ACPI object, coreboot needs the minimal and
nominal core speed values which are specific to the CPU and not only the
CPU family. Since this is done by an undocumented mechanism, FSP has to
do this and puts the information we need into a HOB. This adds the HOB
GUID and the structure of the HOB data.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Change-Id: Ibf338c32de367a3fd57695873da1625338fa196d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66549
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/vendorcode/amd/fsp/cezanne/FspGuids.h | 4 | ||||
| -rw-r--r-- | src/vendorcode/amd/fsp/cezanne/ccx_cppc_data.h | 17 | ||||
| -rw-r--r-- | src/vendorcode/amd/fsp/mendocino/FspGuids.h | 4 | ||||
| -rw-r--r-- | src/vendorcode/amd/fsp/mendocino/ccx_cppc_data.h | 17 |
4 files changed, 42 insertions, 0 deletions
diff --git a/src/vendorcode/amd/fsp/cezanne/FspGuids.h b/src/vendorcode/amd/fsp/cezanne/FspGuids.h index 0eca78e711..1bef794418 100644 --- a/src/vendorcode/amd/fsp/cezanne/FspGuids.h +++ b/src/vendorcode/amd/fsp/cezanne/FspGuids.h @@ -17,4 +17,8 @@ GUID_INIT(0X6D5CD69D, 0XFB24, 0X4461, \ 0XAA, 0X32, 0X8E, 0XE1, 0XB3, 0X3, 0X31, 0X9C ) +#define AMD_FSP_CCX_CPPC_DATA_HOB_GUID \ + GUID_INIT(0x3060C5EC, 0x7399, 0x432D, \ + 0xBC, 0x97, 0xBF, 0x95, 0xE4, 0x3D, 0x53, 0x0C ) + #endif /* __FSP_GUIDS__ */ diff --git a/src/vendorcode/amd/fsp/cezanne/ccx_cppc_data.h b/src/vendorcode/amd/fsp/cezanne/ccx_cppc_data.h new file mode 100644 index 0000000000..a924eaa4d4 --- /dev/null +++ b/src/vendorcode/amd/fsp/cezanne/ccx_cppc_data.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef CEZANNE_FSP_CCX_CPPC_DATA_H +#define CEZANNE_FSP_CCX_CPPC_DATA_H + +#include <types.h> + +#define FSP_CCX_CPPC_DATA_VERSION 1 + +struct fsp_ccx_cppc_data { + uint8_t version; + uint8_t unused[3]; + uint32_t ccx_cppc_min_speed; + uint32_t ccx_cppc_nom_speed; +} __packed; + +#endif /* CEZANNE_FSP_CCX_CPPC_DATA_H */ diff --git a/src/vendorcode/amd/fsp/mendocino/FspGuids.h b/src/vendorcode/amd/fsp/mendocino/FspGuids.h index 0eca78e711..1bef794418 100644 --- a/src/vendorcode/amd/fsp/mendocino/FspGuids.h +++ b/src/vendorcode/amd/fsp/mendocino/FspGuids.h @@ -17,4 +17,8 @@ GUID_INIT(0X6D5CD69D, 0XFB24, 0X4461, \ 0XAA, 0X32, 0X8E, 0XE1, 0XB3, 0X3, 0X31, 0X9C ) +#define AMD_FSP_CCX_CPPC_DATA_HOB_GUID \ + GUID_INIT(0x3060C5EC, 0x7399, 0x432D, \ + 0xBC, 0x97, 0xBF, 0x95, 0xE4, 0x3D, 0x53, 0x0C ) + #endif /* __FSP_GUIDS__ */ diff --git a/src/vendorcode/amd/fsp/mendocino/ccx_cppc_data.h b/src/vendorcode/amd/fsp/mendocino/ccx_cppc_data.h new file mode 100644 index 0000000000..76c85bc372 --- /dev/null +++ b/src/vendorcode/amd/fsp/mendocino/ccx_cppc_data.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SABRINA_FSP_CCX_CPPC_DATA_H +#define SABRINA_FSP_CCX_CPPC_DATA_H + +#include <types.h> + +#define FSP_CCX_CPPC_DATA_VERSION 1 + +struct fsp_ccx_cppc_data { + uint8_t version; + uint8_t unused[3]; + uint32_t ccx_cppc_min_speed; + uint32_t ccx_cppc_nom_speed; +} __packed; + +#endif /* SABRINA_FSP_CCX_CPPC_DATA_H */ |