diff options
| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2021-12-01 14:33:25 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-12-23 14:42:28 +0000 |
| commit | b647e35119c10099b78609f432a7cb9ad3e7e1e2 (patch) | |
| tree | 05ac083ee18ac5a3d513d33ae4d6a3366127628a /src | |
| parent | 84cd7c351f1dd1afb08365ec51dad7ed356be848 (diff) | |
soc/intel/alderlake: Add timestamp for cse_fw_sync
The patch add timestamp around cse_fw_sync().
TEST=Verified on Brya, cbmem -t:
948:starting CSE firmware sync 1,381,577 (45,227)
949:finished CSE firmware sync 1,459,513 (77,936)
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Idba11417e0fc7c18d0d938a4293ec3aff1537fb4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/alderlake/romstage/romstage.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index b9d08c8386..ae83d49275 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -16,6 +16,7 @@ #include <soc/romstage.h> #include <soc/soc_chip.h> #include <cpu/intel/cpu_ids.h> +#include <timestamp.h> #include <string.h> #define FSP_SMBIOS_MEMORY_INFO_GUID \ @@ -135,8 +136,11 @@ void mainboard_romstage_entry(void) s3wake = pmc_fill_power_state(ps) == ACPI_S3; - if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && !s3wake) + if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && !s3wake) { + timestamp_add_now(TS_START_CSE_FW_SYNC); cse_fw_sync(); + timestamp_add_now(TS_END_CSE_FW_SYNC); + } /* * Set low maximum temp threshold value used for dynamic thermal sensor |