diff options
| author | Tim Chen <tim-chen@quanta.corp-partner.google.com> | 2020-04-20 16:26:30 +0800 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2020-04-23 06:54:14 +0000 |
| commit | b26f792d7231a6ed16976366a4f58f23077eb5d9 (patch) | |
| tree | 67d5e5b164b7ed1f913583b3bb32e2c3227dd8ac /src | |
| parent | 21a4053fde87801b42a0de39d5b6536c1ed4b475 (diff) | |
mb/google/puff: Switch USB2 port1 and port3
Switch USB2 port1 and port3 for duffy and kaisa due to circuit change.
BUG=b:153682207, b:154451230, b:154445635
BRANCH=None
TEST=emerge-puff coreboot chromeos-bootimage
boot on puff board
Change-Id: I9c0cbcbefd045085fb70cf4f41869ab9b98103c4
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/hatch/variants/duffy/overridetree.cb | 14 | ||||
| -rw-r--r-- | src/mainboard/google/hatch/variants/kaisa/overridetree.cb | 14 |
2 files changed, 14 insertions, 14 deletions
diff --git a/src/mainboard/google/hatch/variants/duffy/overridetree.cb b/src/mainboard/google/hatch/variants/duffy/overridetree.cb index 2f36bc8b62..ade12c5806 100644 --- a/src/mainboard/google/hatch/variants/duffy/overridetree.cb +++ b/src/mainboard/google/hatch/variants/duffy/overridetree.cb @@ -22,23 +22,23 @@ chip soc/intel/cannonlake # USB configuration register "usb2_ports[0]" = "USB2_PORT_MID(OC2)" # Type-A Port 2 - register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port - register "usb2_ports[2]" = "{ + register "usb2_ports[1]" = "{ .enable = 1, - .ocpin = OC3, + .ocpin = OC1, .tx_bias = USB2_BIAS_0MV, .tx_emp_enable = USB2_PRE_EMP_ON, .pre_emp_bias = USB2_BIAS_28P15MV, .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 3 - register "usb2_ports[3]" = "{ + }" # Type-A Port 1 + register "usb2_ports[2]" = "{ .enable = 1, - .ocpin = OC1, + .ocpin = OC3, .tx_bias = USB2_BIAS_0MV, .tx_emp_enable = USB2_PRE_EMP_ON, .pre_emp_bias = USB2_BIAS_28P15MV, .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 1 + }" # Type-A Port 3 + register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port register "usb2_ports[4]" = "{ .enable = 1, .ocpin = OC_SKIP, diff --git a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb index db05302278..e2380f4460 100644 --- a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb @@ -22,23 +22,23 @@ chip soc/intel/cannonlake # USB configuration register "usb2_ports[0]" = "USB2_PORT_MID(OC2)" # Type-A Port 2 - register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port - register "usb2_ports[2]" = "{ + register "usb2_ports[1]" = "{ .enable = 1, - .ocpin = OC3, + .ocpin = OC1, .tx_bias = USB2_BIAS_0MV, .tx_emp_enable = USB2_PRE_EMP_ON, .pre_emp_bias = USB2_BIAS_28P15MV, .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 3 - register "usb2_ports[3]" = "{ + }" # Type-A Port 1 + register "usb2_ports[2]" = "{ .enable = 1, - .ocpin = OC1, + .ocpin = OC3, .tx_bias = USB2_BIAS_0MV, .tx_emp_enable = USB2_PRE_EMP_ON, .pre_emp_bias = USB2_BIAS_28P15MV, .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 1 + }" # Type-A Port 3 + register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port register "usb2_ports[4]" = "{ .enable = 1, .ocpin = OC_SKIP, |