diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2017-09-04 17:10:50 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-09-13 19:00:51 +0000 |
| commit | b00ba2ae6bd9da0f03dfecd63504e92e1e221095 (patch) | |
| tree | db5286fa062958e16de19155a1d6b7f05b324f9e /src | |
| parent | 06766c1efaf7e9f502dc0705f31af0f234824cb7 (diff) | |
amd/stoneyridge: Remove CONFIG_LOGICAL_CPUS setup
Delete the check for sibling cores and the programming of CPUID HTT
and CmpLegacy back-door bits. The code has no effect on modern
Family 15h APUs. The bits being modified come up set out of reset.
Change-Id: Ida76863d84109b49ce6b12c71bad5b44331a2ff9
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/amd/stoneyridge/model_15_init.c | 20 |
1 files changed, 0 insertions, 20 deletions
diff --git a/src/soc/amd/stoneyridge/model_15_init.c b/src/soc/amd/stoneyridge/model_15_init.c index 631e89cb98..7dfcdb81f1 100644 --- a/src/soc/amd/stoneyridge/model_15_init.c +++ b/src/soc/amd/stoneyridge/model_15_init.c @@ -37,9 +37,6 @@ static void model_15_init(device_t dev) u8 i; msr_t msr; int msrno; -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) - u32 siblings; -#endif disable_cache(); /* Enable access to AMD RdDram and WrDram extension bits */ @@ -71,31 +68,14 @@ static void model_15_init(device_t dev) for (i = 0 ; i < 6 ; i++) wrmsr(MCI_STATUS + (i * 4), msr); - /* Enable the local CPU APICs */ setup_lapic(); -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) - siblings = cpuid_ecx(0x80000008) & 0xff; - - if (siblings > 0) { - msr = rdmsr_amd(CPU_ID_FEATURES_MSR); - msr.lo |= 1 << 28; - wrmsr_amd(CPU_ID_FEATURES_MSR, msr); - - msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); - msr.hi |= 1 << (33 - 32); - wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); - } - printk(BIOS_DEBUG, "siblings = %02d, ", siblings); -#endif - /* DisableCf8ExtCfg */ msr = rdmsr(NB_CFG_MSR); msr.hi &= ~(1 << (46 - 32)); wrmsr(NB_CFG_MSR, msr); - /* Write protect SMM space with SMMLOCK. */ msr = rdmsr(HWCR_MSR); msr.lo |= (1 << 0); |