soc/inte/*/gpio; Add GPE_EN and GPE_STS register definition

coreboot needs to set GPE_EN bit for the GPIOs which are wake capable
from s0ix/sleep. Due to GPIO locking mechanism, coreboot/OS will not
be able to write GPE_EN register post GPIO has been locked.

This patch adds support in SoC code to provide correct offset for
GPE_EN and GPE_STS registers to the common code.

Plan is to use this offsets to set GPE_EN bits before GPIO locking
in coreboot which will be part of subsequent CL.

BUG=b:222375516
BRANCH=firmware-brya-14505.B
TEST=Check if code compiles for Brya and correct offset values are printed.

Change-Id: I6b813b30b8b360f8eccbf539b57387310e380560
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>

7 files changed, 40 insertions, 0 deletions

diff --git a/src/soc/intel/alderlake/gpio.c b/src/soc/intel/alderlake/gpio.c
index dc5847d883..69e2982368 100644
--- a/src/soc/intel/alderlake/gpio.c
+++ b/src/soc/intel/alderlake/gpio.c
@@ -109,6 +109,8 @@ static const struct pad_community adl_communities[] = {
 		.host_own_reg_0 = HOSTSW_OWN_REG_0,
 		.gpi_int_sts_reg_0 = GPI_INT_STS_0,
 		.gpi_int_en_reg_0 = GPI_INT_EN_0,
+		.gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
+		.gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
 		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
 		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
@@ -134,6 +136,8 @@ static const struct pad_community adl_communities[] = {
 		.host_own_reg_0 = HOSTSW_OWN_REG_0,
 		.gpi_int_sts_reg_0 = GPI_INT_STS_0,
 		.gpi_int_en_reg_0 = GPI_INT_EN_0,
+		.gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
+		.gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
 		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
 		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
@@ -161,6 +165,8 @@ static const struct pad_community adl_communities[] = {
 		.host_own_reg_0 = HOSTSW_OWN_REG_0,
 		.gpi_int_sts_reg_0 = GPI_INT_STS_0,
 		.gpi_int_en_reg_0 = GPI_INT_EN_0,
+		.gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
+		.gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
 		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
 		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
@@ -181,6 +187,8 @@ static const struct pad_community adl_communities[] = {
 		.host_own_reg_0 = HOSTSW_OWN_REG_0,
 		.gpi_int_sts_reg_0 = GPI_INT_STS_0,
 		.gpi_int_en_reg_0 = GPI_INT_EN_0,
+		.gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
+		.gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
 		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
 		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
@@ -202,6 +210,8 @@ static const struct pad_community adl_communities[] = {
 		.host_own_reg_0 = HOSTSW_OWN_REG_0,
 		.gpi_int_sts_reg_0 = GPI_INT_STS_0,
 		.gpi_int_en_reg_0 = GPI_INT_EN_0,
+		.gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
+		.gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
 		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
 		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
@@ -226,6 +236,8 @@ static const struct pad_community adl_communities[] = {
 		.host_own_reg_0 = HOSTSW_OWN_REG_0,
 		.gpi_int_sts_reg_0 = GPI_INT_STS_0,
 		.gpi_int_en_reg_0 = GPI_INT_EN_0,
+		.gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
+		.gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
 		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
 		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
diff --git a/src/soc/intel/alderlake/include/soc/gpio_defs.h b/src/soc/intel/alderlake/include/soc/gpio_defs.h
index 86021672f4..de520c9884 100644
--- a/src/soc/intel/alderlake/include/soc/gpio_defs.h
+++ b/src/soc/intel/alderlake/include/soc/gpio_defs.h
@@ -344,6 +344,8 @@
 #define HOSTSW_OWN_REG_0			0xb0
 #define GPI_INT_STS_0				0x100
 #define GPI_INT_EN_0				0x110
+#define GPI_GPE_STS_0				0x140
+#define GPI_GPE_EN_0				0x160
 #define GPI_SMI_STS_0				0x180
 #define GPI_SMI_EN_0				0x1A0
 #define PAD_CFG_BASE				0x700
diff --git a/src/soc/intel/cannonlake/gpio.c b/src/soc/intel/cannonlake/gpio.c
index 90efacc3f3..0e8c4f1bf5 100644
--- a/src/soc/intel/cannonlake/gpio.c
+++ b/src/soc/intel/cannonlake/gpio.c
@@ -74,6 +74,8 @@ static const struct pad_community cnl_communities[TOTAL_GPIO_COMM] = {
 		.host_own_reg_0 = HOSTSW_OWN_REG_0,
 		.gpi_int_sts_reg_0 = GPI_INT_STS_0,
 		.gpi_int_en_reg_0 = GPI_INT_EN_0,
+		.gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
+		.gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
 		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
 		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 		.gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
@@ -96,6 +98,8 @@ static const struct pad_community cnl_communities[TOTAL_GPIO_COMM] = {
 		.host_own_reg_0 = HOSTSW_OWN_REG_0,
 		.gpi_int_sts_reg_0 = GPI_INT_STS_0,
 		.gpi_int_en_reg_0 = GPI_INT_EN_0,
+		.gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
+		.gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
 		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
 		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 		.gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
@@ -118,6 +122,8 @@ static const struct pad_community cnl_communities[TOTAL_GPIO_COMM] = {
 		.host_own_reg_0 = HOSTSW_OWN_REG_0,
 		.gpi_int_sts_reg_0 = GPI_INT_STS_0,
 		.gpi_int_en_reg_0 = GPI_INT_EN_0,
+		.gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
+		.gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
 		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
 		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 		.gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
@@ -140,6 +146,8 @@ static const struct pad_community cnl_communities[TOTAL_GPIO_COMM] = {
 		.host_own_reg_0 = HOSTSW_OWN_REG_0,
 		.gpi_int_sts_reg_0 = GPI_INT_STS_0,
 		.gpi_int_en_reg_0 = GPI_INT_EN_0,
+		.gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
+		.gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
 		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
 		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 		.gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
@@ -162,6 +170,8 @@ static const struct pad_community cnl_communities[TOTAL_GPIO_COMM] = {
 		.host_own_reg_0 = HOSTSW_OWN_REG_0,
 		.gpi_int_sts_reg_0 = GPI_INT_STS_0,
 		.gpi_int_en_reg_0 = GPI_INT_EN_0,
+		.gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
+		.gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
 		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
 		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 		.gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_defs.h
index c96a67d69d..2ee078d54a 100644
--- a/src/soc/intel/cannonlake/include/soc/gpio_defs.h
+++ b/src/soc/intel/cannonlake/include/soc/gpio_defs.h
@@ -234,6 +234,8 @@
 #define HOSTSW_OWN_REG_0			0xb0
 #define GPI_INT_STS_0				0x100
 #define GPI_INT_EN_0				0x120
+#define GPI_GPE_STS_0				0x140
+#define GPI_GPE_EN_0				0x160
 #define GPI_SMI_STS_0				0x180
 #define GPI_SMI_EN_0				0x1A0
 #define GPI_NMI_STS_0				0x1c0
diff --git a/src/soc/intel/common/block/include/intelblocks/gpio.h b/src/soc/intel/common/block/include/intelblocks/gpio.h
index d5cc8fe9c5..5043c84c2b 100644
--- a/src/soc/intel/common/block/include/intelblocks/gpio.h
+++ b/src/soc/intel/common/block/include/intelblocks/gpio.h
@@ -126,6 +126,8 @@ struct pad_community {
 	uint16_t	gpi_int_en_reg_0; /* offset to GPI Int Enable Reg 0 */
 	uint16_t	gpi_smi_sts_reg_0; /* offset to GPI SMI STS Reg 0 */
 	uint16_t	gpi_smi_en_reg_0; /* offset to GPI SMI EN Reg 0 */
+	uint16_t	gpi_gpe_sts_reg_0; /* offset to GPI GPE STS Reg 0 */
+	uint16_t	gpi_gpe_en_reg_0; /* offset to GPI GPE EN Reg 0 */
 	uint16_t	gpi_nmi_sts_reg_0; /* offset to GPI NMI STS Reg 0 */
 	uint16_t	gpi_nmi_en_reg_0; /* offset to GPI NMI EN Reg 0 */
 	uint16_t	pad_cfg_base; /* offset to first PAD_GFG_DW0 Reg */
diff --git a/src/soc/intel/tigerlake/gpio.c b/src/soc/intel/tigerlake/gpio.c
index 9a37117072..3fd8bfb97c 100644
--- a/src/soc/intel/tigerlake/gpio.c
+++ b/src/soc/intel/tigerlake/gpio.c
@@ -97,6 +97,8 @@ static const struct pad_community tgl_communities[] = {
 		.host_own_reg_0 = HOSTSW_OWN_REG_0,
 		.gpi_int_sts_reg_0 = GPI_INT_STS_0,
 		.gpi_int_en_reg_0 = GPI_INT_EN_0,
+		.gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
+		.gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
 		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
 		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 		.gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
@@ -122,6 +124,8 @@ static const struct pad_community tgl_communities[] = {
 		.host_own_reg_0 = HOSTSW_OWN_REG_0,
 		.gpi_int_sts_reg_0 = GPI_INT_STS_0,
 		.gpi_int_en_reg_0 = GPI_INT_EN_0,
+		.gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
+		.gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
 		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
 		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 		.gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
@@ -146,6 +150,8 @@ static const struct pad_community tgl_communities[] = {
 		.host_own_reg_0 = HOSTSW_OWN_REG_0,
 		.gpi_int_sts_reg_0 = GPI_INT_STS_0,
 		.gpi_int_en_reg_0 = GPI_INT_EN_0,
+		.gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
+		.gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
 		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
 		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 		.gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
@@ -168,6 +174,8 @@ static const struct pad_community tgl_communities[] = {
 		.host_own_reg_0 = HOSTSW_OWN_REG_0,
 		.gpi_int_sts_reg_0 = GPI_INT_STS_0,
 		.gpi_int_en_reg_0 = GPI_INT_EN_0,
+		.gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
+		.gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
 		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
 		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 		.gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
@@ -193,6 +201,8 @@ static const struct pad_community tgl_communities[] = {
 		.host_own_reg_0 = HOSTSW_OWN_REG_0,
 		.gpi_int_sts_reg_0 = GPI_INT_STS_0,
 		.gpi_int_en_reg_0 = GPI_INT_EN_0,
+		.gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
+		.gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
 		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
 		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 		.gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
diff --git a/src/soc/intel/tigerlake/include/soc/gpio_defs.h b/src/soc/intel/tigerlake/include/soc/gpio_defs.h
index 2f404393a0..fd6141e2ef 100644
--- a/src/soc/intel/tigerlake/include/soc/gpio_defs.h
+++ b/src/soc/intel/tigerlake/include/soc/gpio_defs.h
@@ -290,6 +290,8 @@
 #define HOSTSW_OWN_REG_0			0xb0
 #define GPI_INT_STS_0				0x100
 #define GPI_INT_EN_0				0x120
+#define GPI_GPE_STS_0				0x140
+#define GPI_GPE_EN_0				0x160
 #define GPI_SMI_STS_0				0x180
 #define GPI_SMI_EN_0				0x1A0
 #define GPI_NMI_STS_0				0x1c0