diff options
| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2022-03-16 23:36:30 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-04-06 17:34:25 +0000 |
| commit | afe5562ca39b26cc42ca04da55b68f73a7b70654 (patch) | |
| tree | 27fda5c9857266cf70608c76a1a0cf812196a983 /src | |
| parent | fad76f33a9be2b629266f4f4276345970a1b6ebd (diff) | |
soc/intel/(cnl, jsl, tgl): Enable SOC_INTEL_COMMON_BASECODE
The patch SOC_INTEL_COMMON_BASECODE Kconfig for Comet Lake, Jasper Lake
and Tiger Lake SoCs. It allows access to intelbasecode/debug_feature.h
for Comet Lake, Jasper Lake and Tiger Lake SoCs.
TEST=Build code for Brya
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ie55ded673c8fa0edf2ca6789b15771bd2e56c95e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/cannonlake/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/jasperlake/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/Kconfig | 1 |
3 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 0a6138155e..ddb16198aa 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -26,6 +26,7 @@ config SOC_INTEL_COMETLAKE select PMC_IPC_ACPI_INTERFACE if DISABLE_HECI1_AT_PRE_BOOT select SOC_INTEL_CONFIGURE_DDI_A_4_LANES select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC if DISABLE_HECI1_AT_PRE_BOOT + select SOC_INTEL_COMMON_BASECODE if SOC_INTEL_CSE_LITE_SKU config SOC_INTEL_COMETLAKE_1 bool diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index e0e0c7b60b..53b020176a 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -69,6 +69,7 @@ config CPU_SPECIFIC_OPTIONS select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE + select SOC_INTEL_COMMON_BASECODE if SOC_INTEL_CSE_LITE_SKU config DCACHE_RAM_BASE default 0xfef00000 diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 265aa5f23a..c0cf683d2c 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -88,6 +88,7 @@ config CPU_SPECIFIC_OPTIONS select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE + select SOC_INTEL_COMMON_BASECODE if SOC_INTEL_CSE_LITE_SKU config MAX_CPUS int |