diff options
| author | Keith Hui <buurin@gmail.com> | 2023-07-29 11:08:09 -0400 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-11-13 20:31:49 +0000 |
| commit | adaeb1102186c8dad56f9feee01ec2189e2d7778 (patch) | |
| tree | 9b40bd2da619c424798b9fbbb7b2e3cca70a3671 /src | |
| parent | 45e4ab4a660cb7ce312f2d11a153f2d9ef4158da (diff) | |
nb/intel/sandybridge: Clean up post Haswell SPD mapping API migration
With migration to Haswell SPD mapping interface complete:
1. Remove weak stubs meant to ensure smooth transition and
internalizes mainboard_get_spd() within raminit.c.
2. Remove post-mainboard SPD data sanitization code in raminit_mrc.c,
now that it fills its own SPD data.
3. Remove old prototypes from raminit_native.h
4a. Drops raminit_native.h from raminit.c, as individual headers
therein are already included.
4b. Drop another header from raminit.c IWYU identified as unneeded.
asus/p8z77-m still builds afterwards.
(sandybridge to receive a full IWYU cleanup later.)
Change-Id: Ie073c1386cd0a645069f0e1416263b4fa359b74b
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76991
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit.c | 9 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_mrc.c | 16 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_native.h | 4 |
3 files changed, 2 insertions, 27 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 2575a9c6fc..085292bb22 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> -#include <commonlib/region.h> #include <cf9_reset.h> #include <string.h> #include <cbfs.h> @@ -20,7 +19,6 @@ #include <types.h> #include "raminit.h" -#include "raminit_native.h" #include "raminit_common.h" #include "sandybridge.h" #include "chip.h" @@ -140,7 +138,7 @@ static int verify_crc16_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) return match; } -void read_spd(spd_raw_data * spd, u8 addr, bool id_only) +static void read_spd(spd_raw_data *spd, u8 addr, bool id_only) { int j; if (id_only) { @@ -152,10 +150,7 @@ void read_spd(spd_raw_data * spd, u8 addr, bool id_only) } } -/* Temporary stub */ -__weak void mb_get_spd_map(struct spd_info *spdi) {} - -__weak void mainboard_get_spd(spd_raw_data *spd, bool id_only) +static void mainboard_get_spd(spd_raw_data *spd, bool id_only) { const struct northbridge_intel_sandybridge_config *cfg = config_of_soc(); unsigned int i; diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index de41ae590f..a1805a2ada 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -312,9 +312,6 @@ static void devicetree_fill_pei_data(struct pei_data *pei_data) pei_data->usb3.xhci_streams = cfg->usb3.xhci_streams; } -/* Temporary stub */ -__weak void mb_get_spd_map(struct spd_info *spdi) {} - static void spd_fill_pei_data(struct pei_data *pei_data) { struct spd_info spdi = {0}; @@ -397,19 +394,6 @@ void perform_raminit(int s3resume) (!pei_data.spd_addresses[2] && !pei_data.spd_data[2][0]) + (!pei_data.spd_addresses[3] && !pei_data.spd_data[3][0]) * 2; - /* Fix spd_data. MRC only uses spd_data[0] and ignores the other */ - for (size_t i = 1; i < ARRAY_SIZE(pei_data.spd_data); i++) { - if (pei_data.spd_data[i][0] && !pei_data.spd_data[0][0]) { - memcpy(pei_data.spd_data[0], pei_data.spd_data[i], - sizeof(pei_data.spd_data[0])); - - } else if (pei_data.spd_data[i][0] && pei_data.spd_data[0][0]) { - if (memcmp(pei_data.spd_data[i], pei_data.spd_data[0], - sizeof(pei_data.spd_data[0])) != 0) - die("Onboard SPDs must match each other"); - } - } - disable_p2p(); pei_data.boot_mode = s3resume ? 2 : 0; diff --git a/src/northbridge/intel/sandybridge/raminit_native.h b/src/northbridge/intel/sandybridge/raminit_native.h index 22aea5b508..fa0f2ffeaa 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.h +++ b/src/northbridge/intel/sandybridge/raminit_native.h @@ -8,8 +8,4 @@ #include <stdbool.h> #include <stdint.h> -/* The order is: ch0dimmA, ch0dimmB, ch1dimmA, ch1dimmB */ -void read_spd(spd_raw_data *spd, u8 addr, bool id_only); -void mainboard_get_spd(spd_raw_data *spd, bool id_only); - #endif /* RAMINIT_NATIVE_H */ |