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authorAngel Pons <th3fanbus@gmail.com>2020-11-05 11:35:54 +0100
committerAngel Pons <th3fanbus@gmail.com>2020-11-07 14:20:38 +0000
commita575759c401d7bebaeb8909d5bce6a78edfb0bb4 (patch)
treebf4e7d5267fb1acf3c4d32631d03cc33943f0214 /src
parent1464a059332c7f9ff9a80455309265bb285c58c8 (diff)
sb/intel/lynxpoint/pcie.c: Ensure OBFF is disabled
Setting registers 64h[19:18] = 2 and 68h[14:13] = 3 enables OBFF, and setting registers 64h[19:18] = 0 and 68h[14:13] = 0 disables OBFF. Register at offset 0x64 is DCAP2, and offset 0x68 is DCTL2. However, current code doesn't account for this. The result is that register 64h[19:18] = 2 and 68h[14:13] = 0, which means the hardware is OBFF-capable but support is disabled, which makes no sense. Given that reference code and Broadwell both disable OBFF, disable it here too. Change-Id: I6c1cafdb435ee22909b077128b3ae5bde5543039 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src')
-rw-r--r--src/southbridge/intel/lynxpoint/pcie.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c
index 4a245b1899..19eb9fa396 100644
--- a/src/southbridge/intel/lynxpoint/pcie.c
+++ b/src/southbridge/intel/lynxpoint/pcie.c
@@ -645,9 +645,9 @@ static void pch_pcie_early(struct device *dev)
pci_and_config32(dev, 0x338, ~(1 << 26));
}
- /* Enable LTR in Root Port. */
- pci_or_config32(dev, 0x64, 1 << 11);
- pci_update_config32(dev, 0x68, ~(1 << 10), (1 << 10));
+ /* Enable LTR in Root Port. Disable OBFF. */
+ pci_update_config32(dev, 0x64, ~(3 << 18), 1 << 11);
+ pci_update_config16(dev, 0x68, ~(3 << 13), 1 << 10);
pci_update_config32(dev, 0x318, ~(0xffff << 16), (0x1414 << 16));