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authorAaron Durbin <adurbin@chromium.org>2016-04-19 15:17:08 -0500
committerAaron Durbin <adurbin@chromium.org>2016-04-21 20:40:40 +0200
commita0546da57a79499662f9f82590d1ef6fa18ed893 (patch)
treefa5f47834631ff9b9310592acb2590d1c353d56b /src
parent0eb1f1cba9080f2ab11d5492842f4d3c3c09af17 (diff)
arch: use Kconfig variable for coreboot table size
Instead of hard coding a #define in each architecture's tables.c for the coreboot table size in cbmem use a Kconfig varible. This aids in aligning on a common write_tables() implementation instead of duplicating the code for each architecture. Change-Id: I09c0f56133606ea62e9a9c4c6b9828bc24dcc668 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14429 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/Kconfig9
-rw-r--r--src/arch/arm/tables.c2
-rw-r--r--src/arch/arm64/tables.c2
-rw-r--r--src/arch/mips/tables.c2
-rw-r--r--src/arch/power8/tables.c2
-rw-r--r--src/arch/riscv/tables.c2
-rw-r--r--src/arch/x86/tables.c3
7 files changed, 16 insertions, 6 deletions
diff --git a/src/Kconfig b/src/Kconfig
index f9bd661e05..b656bbfa22 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -658,6 +658,15 @@ config ACPI_NHLT
help
Build support for NHLT (non HD Audio) ACPI table generation.
+
+config COREBOOT_TABLE_SIZE
+ hex
+ default 0x8000 if ARCH_X86
+ default 0x2000 if !ARCH_X86
+ help
+ The amount of memory to reserve for the coreboot tables in
+ cbmem.
+
#These Options are here to avoid "undefined" warnings.
#The actual selection and help texts are in the following menu.
diff --git a/src/arch/arm/tables.c b/src/arch/arm/tables.c
index f2d0c86db9..17a3fd1647 100644
--- a/src/arch/arm/tables.c
+++ b/src/arch/arm/tables.c
@@ -23,7 +23,7 @@
#include <cbmem.h>
#include <lib.h>
-#define MAX_COREBOOT_TABLE_SIZE (8 * 1024)
+#define MAX_COREBOOT_TABLE_SIZE CONFIG_COREBOOT_TABLE_SIZE
void write_tables(void)
{
diff --git a/src/arch/arm64/tables.c b/src/arch/arm64/tables.c
index f2d0c86db9..17a3fd1647 100644
--- a/src/arch/arm64/tables.c
+++ b/src/arch/arm64/tables.c
@@ -23,7 +23,7 @@
#include <cbmem.h>
#include <lib.h>
-#define MAX_COREBOOT_TABLE_SIZE (8 * 1024)
+#define MAX_COREBOOT_TABLE_SIZE CONFIG_COREBOOT_TABLE_SIZE
void write_tables(void)
{
diff --git a/src/arch/mips/tables.c b/src/arch/mips/tables.c
index 717b7fdfc0..2083442f29 100644
--- a/src/arch/mips/tables.c
+++ b/src/arch/mips/tables.c
@@ -24,7 +24,7 @@
#include <cbmem.h>
#include <lib.h>
-#define MAX_COREBOOT_TABLE_SIZE (8 * 1024)
+#define MAX_COREBOOT_TABLE_SIZE CONFIG_COREBOOT_TABLE_SIZE
void write_tables(void)
{
diff --git a/src/arch/power8/tables.c b/src/arch/power8/tables.c
index b5bc9ab770..0a885053a0 100644
--- a/src/arch/power8/tables.c
+++ b/src/arch/power8/tables.c
@@ -23,7 +23,7 @@
#include <cbmem.h>
#include <lib.h>
-#define MAX_COREBOOT_TABLE_SIZE (8 * 1024)
+#define MAX_COREBOOT_TABLE_SIZE CONFIG_COREBOOT_TABLE_SIZE
void write_tables(void)
{
diff --git a/src/arch/riscv/tables.c b/src/arch/riscv/tables.c
index f2d0c86db9..17a3fd1647 100644
--- a/src/arch/riscv/tables.c
+++ b/src/arch/riscv/tables.c
@@ -23,7 +23,7 @@
#include <cbmem.h>
#include <lib.h>
-#define MAX_COREBOOT_TABLE_SIZE (8 * 1024)
+#define MAX_COREBOOT_TABLE_SIZE CONFIG_COREBOOT_TABLE_SIZE
void write_tables(void)
{
diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c
index 86e2b236a1..8cfd6555a0 100644
--- a/src/arch/x86/tables.c
+++ b/src/arch/x86/tables.c
@@ -26,6 +26,8 @@
#include <cbmem.h>
#include <smbios.h>
+#define MAX_COREBOOT_TABLE_SIZE CONFIG_COREBOOT_TABLE_SIZE
+
void write_tables(void)
{
unsigned long low_table_start, low_table_end;
@@ -181,7 +183,6 @@ void write_tables(void)
post_code(0x9e);
-#define MAX_COREBOOT_TABLE_SIZE (32 * 1024)
post_code(0x9d);
high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE, MAX_COREBOOT_TABLE_SIZE);