diff options
| author | Subrata Banik <subratabanik@google.com> | 2023-09-22 12:45:45 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-09-23 09:25:56 +0000 |
| commit | 9c58830a23efff2f90279d05a839e0892d849e1b (patch) | |
| tree | 73f68b960caf53c3805daa062a896192ba28a5f3 /src | |
| parent | 17d619c25ac4a1ce75a0ad7565b1cdb9de50cf5b (diff) | |
soc/intel/meteorlake: Hook up UPD LowerBasicMemTestSize
Hook the newly exposed LowerBasicMemTestSize UPD up so that boards
can configure it via devicetree.
BUG=b:301441204
TEST=Verified by enabling/disabling the UPD on google/rex.
Change-Id: Iec466aeaebd72f222d97f720a85bbb8c27e26325
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78066
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/meteorlake/chip.h | 7 | ||||
| -rw-r--r-- | src/soc/intel/meteorlake/romstage/fsp_params.c | 1 |
2 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h index 2c3ec030c8..ec38e80f05 100644 --- a/src/soc/intel/meteorlake/chip.h +++ b/src/soc/intel/meteorlake/chip.h @@ -439,6 +439,13 @@ struct soc_intel_meteorlake_config { /* Gear Selection for SAGV points. 0: Auto, 1: Gear 1, 2: Gear 2, 4: Gear 4 */ uint8_t sagv_gear[MAX_SAGV_POINTS]; + + /* + * Enable or Disable Reduced BasicMemoryTest size. + * Default is set to 0. + * Set this to 1 in order to reduce BasicMemoryTest size + */ + bool lower_basic_mem_test_size; }; typedef struct soc_intel_meteorlake_config config_t; diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index 2a07753abc..d53a0d4da0 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -158,6 +158,7 @@ static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg, m_cfg->RMT = config->rmt; /* Enable MRC Fast Boot */ m_cfg->MrcFastBoot = 1; + m_cfg->LowerBasicMemTestSize = config->lower_basic_mem_test_size; } static void fill_fspm_cpu_params(FSP_M_CONFIG *m_cfg, |