soc/intel/cannonlake: Install common i2c

Add common i2c support for cannonlake.

TEST=N/A

Change-Id: I5c60b0579f9e6050308896dcb13dda0bbb724d2b
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22238
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

4 files changed, 92 insertions, 0 deletions

diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index ee4fcbec78..4047a38fb2 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -52,6 +52,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_BLOCK_GPIO
 	select SOC_INTEL_COMMON_BLOCK_GSPI
 	select SOC_INTEL_COMMON_BLOCK_ITSS
+	select SOC_INTEL_COMMON_BLOCK_I2C
 	select SOC_INTEL_COMMON_BLOCK_LPC
 	select SOC_INTEL_COMMON_BLOCK_LPSS
 	select SOC_INTEL_COMMON_BLOCK_P2SB
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc
index 194291e586..de137f629a 100644
--- a/src/soc/intel/cannonlake/Makefile.inc
+++ b/src/soc/intel/cannonlake/Makefile.inc
@@ -15,12 +15,14 @@ bootblock-y += pmutil.c
 bootblock-y += bootblock/report_platform.c
 bootblock-y += gpio.c
 bootblock-y += gspi.c
+bootblock-y += i2c.c
 bootblock-y += memmap.c
 bootblock-y += spi.c
 bootblock-$(CONFIG_UART_DEBUG) += uart.c
 
 romstage-y += gpio.c
 romstage-y += gspi.c
+romstage-y += i2c.c
 romstage-y += memmap.c
 romstage-y += pmutil.c
 romstage-y += reset.c
@@ -35,6 +37,7 @@ ramstage-y += gpio.c
 ramstage-y += graphics.c
 ramstage-y += gspi.c
 ramstage-y += gpio.c
+ramstage-y += i2c.c
 ramstage-y += lpc.c
 ramstage-y += memmap.c
 ramstage-y += pmc.c
@@ -61,6 +64,7 @@ postcar-y += spi.c
 postcar-$(CONFIG_UART_DEBUG) += uart.c
 
 verstage-y += gspi.c
+verstage-y += i2c.c
 verstage-y += pmutil.c
 verstage-y += spi.c
 verstage-$(CONFIG_UART_DEBUG) += uart.c
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 9117d13ed6..9d6f594e87 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -19,6 +19,7 @@
 #define _SOC_CHIP_H_
 
 #include <intelblocks/gspi.h>
+#include <intelblocks/lpss_i2c.h>
 #include <stdint.h>
 #include <soc/pch.h>
 #include <soc/gpio_defs.h>
@@ -27,6 +28,8 @@
 #include <soc/usb.h>
 #include <soc/vr_config.h>
 
+#define CANNONLAKE_I2C_DEV_MAX	6
+
 struct soc_intel_cannonlake_config {
 	/* GSPI */
 	struct gspi_cfg gspi[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
@@ -250,6 +253,9 @@ struct soc_intel_cannonlake_config {
 
 	/* GPIO SD card detect pin */
 	unsigned int sdcard_cd_gpio;
+
+	/* I2C bus configuration */
+	struct lpss_i2c_bus_config i2c[CANNONLAKE_I2C_DEV_MAX];
 };
 
 typedef struct soc_intel_cannonlake_config config_t;
diff --git a/src/soc/intel/cannonlake/i2c.c b/src/soc/intel/cannonlake/i2c.c
new file mode 100644
index 0000000000..b0c35238ee
--- /dev/null
+++ b/src/soc/intel/cannonlake/i2c.c
@@ -0,0 +1,81 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <intelblocks/lpss_i2c.h>
+#include <soc/iomap.h>
+#include <soc/pci_devs.h>
+#include "chip.h"
+
+const struct lpss_i2c_bus_config *i2c_get_soc_cfg(unsigned int bus,
+					const struct device *dev)
+{
+	const struct soc_intel_cannonlake_config *config;
+	if (!dev || !dev->chip_info) {
+		printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",
+		       __func__);
+		return NULL;
+	}
+
+	config = dev->chip_info;
+
+	return &config->i2c[bus];
+}
+
+uintptr_t i2c_get_soc_early_base(unsigned int bus)
+{
+	return EARLY_I2C_BASE(bus);
+}
+
+int i2c_soc_devfn_to_bus(unsigned int devfn)
+{
+	switch (devfn) {
+	case PCH_DEVFN_I2C0:
+		return 0;
+	case PCH_DEVFN_I2C1:
+		return 1;
+	case PCH_DEVFN_I2C2:
+		return 2;
+	case PCH_DEVFN_I2C3:
+		return 3;
+	case PCH_DEVFN_I2C4:
+		return 4;
+	case PCH_DEVFN_I2C5:
+		return 5;
+	}
+	return -1;
+}
+
+int i2c_soc_bus_to_devfn(unsigned int bus)
+{
+	switch (bus) {
+	case 0:
+		return PCH_DEVFN_I2C0;
+	case 1:
+		return PCH_DEVFN_I2C1;
+	case 2:
+		return PCH_DEVFN_I2C2;
+	case 3:
+		return PCH_DEVFN_I2C3;
+	case 4:
+		return PCH_DEVFN_I2C4;
+	case 5:
+		return PCH_DEVFN_I2C5;
+	}
+	return -1;
+}