diff options
| author | Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com> | 2021-07-15 11:39:01 +0800 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2021-07-26 05:24:08 +0000 |
| commit | 9b6a3a0370ef310c36d5457e8cb0bb752a8418e8 (patch) | |
| tree | c6a2ace81227b591216dd107ff89281edfb77c55 /src | |
| parent | a1509d45451d4f7eb42a2407dd22f82fd19a4312 (diff) | |
mb/google/dedede/var/pirika: Add USB2 PHY parameters
This change adds fine-tuned USB2 PHY parameters for pirika.
BUG=192601233
TEST=Built and verified USB2 eye diagram test result
Signed-off-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com>
Change-Id: Icf9fb41cd0ae40728e4ec5bd72a15ec3c45c963b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/dedede/variants/pirika/overridetree.cb | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/variants/pirika/overridetree.cb b/src/mainboard/google/dedede/variants/pirika/overridetree.cb index b7fef8b6e3..df3fead3d9 100644 --- a/src/mainboard/google/dedede/variants/pirika/overridetree.cb +++ b/src/mainboard/google/dedede/variants/pirika/overridetree.cb @@ -37,7 +37,19 @@ chip soc/intel/jasperlake }" # USB Port Configuration + register "usb2_ports[2]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera + register "usb2_ports[7]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .pre_emp_bias = USB2_BIAS_11P25MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Integrated Bluetooth register "tcc_offset" = "8" # TCC of 97C |