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authorTim Van Patten <timvp@google.com>2022-09-13 10:08:49 -0600
committerFelix Held <felix-coreboot@felixheld.de>2022-09-14 22:12:10 +0000
commit9b3112c875b84a8f060ab1cdacc63475f619f916 (patch)
tree8018a1cbf54c9f67c749c7f130b7d326eb97ce1c /src
parent44e4bf26a19136d389d0ff94bd3d8bdae35c732a (diff)
acpi/soc: Conditionally include dptc.asl
Conditionally include dptc.asl based on the Kconfig value SOC_AMD_COMMON_BLOCK_ACPI_DPTC. BRANCH=none BUG=b:217911928 TEST=Build zork TEST=Build guybrush TEST=Build skyrim TEST=Build majolica Change-Id: Idd94af8e8b2d7973abc0fb939e4600189e21656a Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67620 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/amd/cezanne/acpi/soc.asl2
-rw-r--r--src/soc/amd/mendocino/acpi/soc.asl2
-rw-r--r--src/soc/amd/picasso/acpi/soc.asl2
3 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/acpi/soc.asl b/src/soc/amd/cezanne/acpi/soc.asl
index 7e3a3ee6a8..f8f7a8a7a8 100644
--- a/src/soc/amd/cezanne/acpi/soc.asl
+++ b/src/soc/amd/cezanne/acpi/soc.asl
@@ -27,7 +27,9 @@ Scope(\_SB) {
#include <soc/amd/common/acpi/upep.asl>
+#if CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC)
#include <soc/amd/common/acpi/dptc.asl>
+#endif
#include "rtc_workaround.asl"
diff --git a/src/soc/amd/mendocino/acpi/soc.asl b/src/soc/amd/mendocino/acpi/soc.asl
index 5bce314fc0..91b1444c1d 100644
--- a/src/soc/amd/mendocino/acpi/soc.asl
+++ b/src/soc/amd/mendocino/acpi/soc.asl
@@ -29,7 +29,9 @@ Scope(\_SB) {
#include <soc/amd/common/acpi/upep.asl>
+#if CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC)
#include <soc/amd/common/acpi/dptc.asl>
+#endif
#include "rtc_workaround.asl"
diff --git a/src/soc/amd/picasso/acpi/soc.asl b/src/soc/amd/picasso/acpi/soc.asl
index d9d40c7f65..c4425ebdd8 100644
--- a/src/soc/amd/picasso/acpi/soc.asl
+++ b/src/soc/amd/picasso/acpi/soc.asl
@@ -17,4 +17,6 @@ Device(PCI0) {
/* Add GPIO library */
#include <soc/amd/common/acpi/gpio_bank_lib.asl>
+#if CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC)
#include <soc/amd/common/acpi/dptc.asl>
+#endif