diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-11-11 01:27:24 +0100 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2023-08-13 02:40:53 +0000 |
| commit | 9802f1ee546478eec5dd94817ec9b0070e7ae23d (patch) | |
| tree | de5b1327fd205e44a34ea58543a38502ec11a7cc /src | |
| parent | 55822d9587ef30f82756c313fd8d5e0c2293e82f (diff) | |
nb/intel/sandybridge: Clarify RAM overclock options
Rewrite them to more accurately describe what they are about.
Change-Id: Icb0ac1e592b662bbb81da431ff97af1a00f952c0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/northbridge/intel/sandybridge/Kconfig | 29 |
1 files changed, 18 insertions, 11 deletions
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 01aa11c27c..b7738a2080 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -47,25 +47,32 @@ config USE_NATIVE_RAMINIT System Agent/MRC.bin. You should answer Y. config NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES - bool "Ignore vendor programmed fuses that limit max. DRAM frequency" + bool "[OVERCLOCK] Ignore CAPID fuses that limit max DRAM frequency" default n depends on USE_NATIVE_RAMINIT help - Ignore the mainboard's vendor programmed fuses that might limit the - maximum DRAM frequency. By selecting this option the fuses will be - ignored and the only limits on DRAM frequency are set by RAM's SPD and - hard fuses in southbridge's clockgen. - Disabled by default as it might causes system instability. - Handle with care! + Ignore the CAPID fuses that might limit the maximum DRAM frequency + on overclocking-capable parts. By selecting this option, the fuse + values will be ignored and the only limits on DRAM frequency are + determined by SPD values, per-board devicetree settings and hard + limits in the northbridge's MPLL. Disabled by default as it can + cause instability. + Consider this to be an overclocking option. Handle with care! config NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS - bool "Ignore XMP profile max DIMMs per channel" + bool "[OVERCLOCK] Ignore XMP max DIMMs per channel" default n depends on USE_NATIVE_RAMINIT help - Ignore the max DIMMs per channel restriciton defined in XMP profiles. - Disabled by default as it might cause system instability. - Handle with care! + The more DIMMs are in a channel, the more signal integrity worsens. + Because of this, some DIMMs only support running at XMP timings if + the number of DIMMs in the channel is below a limit. This limit is + usually 1, i.e. there must be no other DIMMs in the channel to use + XMP timings. Otherwise, non-XMP timings are used. + When this option is enabled, the max DIMMs per channel restriction + in XMP is ignored. Depending on available margins, this could work + but it can also result in system instability. + Consider this to be an overclocking option. Handle with care! config NATIVE_RAMINIT_IGNORE_XMP_REQUESTED_VOLTAGE bool "Ignore XMP profile requested voltage" |