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authorArthur Heymans <arthur@aheymans.xyz>2021-01-04 12:22:57 +0100
committerArthur Heymans <arthur@aheymans.xyz>2021-01-24 15:54:13 +0000
commit9789689e41c9f560e1f0f8796485d3a68f7c2cb4 (patch)
treeb4f5450ee01ea110baa773f96ee66feadbb64c26 /src
parentaaa69b621be78f570b9e05f783f1edd0f337e196 (diff)
arch/x86/car.ld: Account for FSP-T reserved area
Tested - on ocp/deltalake: boots (with FSP-T). - qemu/i440fx: BUILD_TIMELESS=1 results in the same binary. Change-Id: I7e364ab039b65766eb95538db6b3507bbfbfb487 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/arch/x86/car.ld8
-rw-r--r--src/drivers/intel/fsp2_0/Kconfig9
2 files changed, 16 insertions, 1 deletions
diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld
index 9f8c2ad045..63145f153e 100644
--- a/src/arch/x86/car.ld
+++ b/src/arch/x86/car.ld
@@ -80,13 +80,19 @@
REGION(asan_shadow, ., _shadow_size, ARCH_POINTER_ALIGN_SIZE)
#endif
_car_unallocated_start = .;
- _car_region_end = . + CONFIG_DCACHE_RAM_SIZE - (. - _car_region_start);
+ _car_region_end = . + CONFIG_DCACHE_RAM_SIZE - (. - _car_region_start)
+ - CONFIG_FSP_T_RESERVED_SIZE;
}
. = _car_region_end;
.car.mrc_var . (NOLOAD) : {
. += CONFIG_DCACHE_RAM_MRC_VAR_SIZE;
}
+. = _car_region_end;
+.car.fspt_reserved . (NOLOAD) : {
+ . += CONFIG_FSP_T_RESERVED_SIZE;
+}
+
#if ENV_BOOTBLOCK
_car_mtrr_end = .;
_car_mtrr_start = _car_region_start;
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
index 96ae282522..056c35cb79 100644
--- a/src/drivers/intel/fsp2_0/Kconfig
+++ b/src/drivers/intel/fsp2_0/Kconfig
@@ -117,6 +117,15 @@ config FSP_CAR
help
Use FSP APIs to initialize & Tear Down the Cache-As-Ram
+config FSP_T_RESERVED_SIZE
+ hex
+ default 0x100 if FSP_CAR
+ default 0x0
+ help
+ This is the size of the area reserved by FSP-T. This is not
+ defined in the FSP specification but in the SOC integration
+ guides.
+
config FSP_M_XIP
bool
default n