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authorSooi, Li Cheng <li.cheng.sooi@intel.com>2017-01-04 17:22:51 +0800
committerAaron Durbin <adurbin@chromium.org>2017-01-19 07:28:15 +0100
commit951ec96f17100692daed8c5316ffa13a7ed387d9 (patch)
treeb5396bfa2b7bc35184ceae46499069aa9d06ba9d /src
parent9b4c888f7bb91ea5034802ab381f87c4c9729ad9 (diff)
soc/intel/skylake: Add SATA interrupt for APIC mode
Add SATA interrupt for APIC mode Change-Id: I9e0682e235715399da2c585174925c89b9116ab3 Signed-off-by: Sooi, Li Cheng <li.cheng.sooi@intel.com> Reviewed-on: https://review.coreboot.org/18130 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/skylake/acpi/pci_irqs.asl2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/acpi/pci_irqs.asl b/src/soc/intel/skylake/acpi/pci_irqs.asl
index 41e1a9d75e..eb10b368eb 100644
--- a/src/soc/intel/skylake/acpi/pci_irqs.asl
+++ b/src/soc/intel/skylake/acpi/pci_irqs.asl
@@ -48,6 +48,8 @@ Name (PICP, Package () {
Package () { 0x0016FFFF, 1, 0, HECI_2_IRQ },
Package () { 0x0016FFFF, 2, 0, IDER_IRQ },
Package () { 0x0016FFFF, 3, 0, KT_IRQ },
+ /* D23: Sata controller */
+ Package () { 0x0017FFFF, 0, 0, SATA_IRQ },
/* D21: SerialIo */
Package () { 0x0015FFFF, 0, 0, LPSS_I2C0_IRQ },
Package () { 0x0015FFFF, 1, 0, LPSS_I2C1_IRQ },