soc/intel/skylake: Clean up code by using common System Agent module

This patch currently contains the SA initialization
required for bootblock phase -
1. Use SOC_INTEL_COMMON_BLOCK_SA kconfig for common SA code.
2. Perform PCIEXBAR programming based on soc configurable
PCIEX_LENGTH_xxxMB
3. Use common systemagent header file.

Change-Id: I0fa0a60f680b9b00b7f26f1875c553612b123a8e
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/18566
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

6 files changed, 10 insertions, 60 deletions

diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index ebdcbe3a24..01083723f8 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -42,6 +42,7 @@ config CPU_SPECIFIC_OPTIONS
 	select PCIEXP_COMMON_CLOCK
 	select PCIEXP_CLK_PM
 	select PCIEXP_L1_SUB_STATE
+	select PCIEX_LENGTH_64MB
 	select REG_SCRIPT
 	select RELOCATABLE_MODULES
 	select RELOCATABLE_RAMSTAGE
@@ -49,6 +50,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON
 	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
 	select SOC_INTEL_COMMON_BLOCK
+	select SOC_INTEL_COMMON_BLOCK_SA
 	select SOC_INTEL_COMMON_BLOCK_XHCI
 	select SOC_INTEL_COMMON_LPSS_I2C
 	select SOC_INTEL_COMMON_NHLT
@@ -147,10 +149,6 @@ config IED_REGION_SIZE
 	hex
 	default 0x400000
 
-config MMCONF_BASE_ADDRESS
-	hex "MMIO Base Address"
-	default 0xe0000000
-
 config MONOTONIC_TIMER_MSR
 	def_bool y
 	select HAVE_MONOTONIC_TIMER
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index 49f818d2ff..f7b4971869 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -15,7 +15,6 @@ bootblock-y += bootblock/i2c.c
 bootblock-y += bootblock/pch.c
 bootblock-y += bootblock/report_platform.c
 bootblock-y += bootblock/smbus.c
-bootblock-y += bootblock/systemagent.c
 bootblock-y += flash_controller.c
 bootblock-$(CONFIG_UART_DEBUG) += bootblock/uart.c
 bootblock-$(CONFIG_UART_DEBUG) += uart_debug.c
diff --git a/src/soc/intel/skylake/bootblock/systemagent.c b/src/soc/intel/skylake/bootblock/systemagent.c
deleted file mode 100644
index e76d4d25e9..0000000000
--- a/src/soc/intel/skylake/bootblock/systemagent.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- * Copyright (C) 2016 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <soc/bootblock.h>
-#include <soc/pci_devs.h>
-#include <soc/systemagent.h>
-
-void bootblock_systemagent_early_init(void)
-{
-	uint32_t reg;
-
-	/*
-	 * The "io" variant of the config access is explicitly used to
-	 * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to
-	 * to true. That way all subsequent non-explicit config accesses use
-	 * MCFG. This code also assumes that bootblock_northbridge_init() is
-	 * the first thing called in the non-asm boot block code. The final
-	 * assumption is that no assembly code is using the
-	 * CONFIG_MMCONF_SUPPORT option to do PCI config acceses.
-	 *
-	 * The PCIEXBAR is assumed to live in the memory mapped IO space under
-	 * 4GiB.
-	 */
-	reg = 0;
-	pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, reg);
-	reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */
-	pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR, reg);
-}
diff --git a/src/soc/intel/skylake/include/soc/bootblock.h b/src/soc/intel/skylake/include/soc/bootblock.h
index df81d3f3fc..f290d0f668 100644
--- a/src/soc/intel/skylake/include/soc/bootblock.h
+++ b/src/soc/intel/skylake/include/soc/bootblock.h
@@ -16,6 +16,8 @@
 #ifndef _SOC_SKYLAKE_BOOTBLOCK_H_
 #define _SOC_SKYLAKE_BOOTBLOCK_H_
 
+#include <intelblocks/systemagent.h>
+
 #if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
 #include <fsp/bootblock.h>
 #else
@@ -25,7 +27,6 @@ static inline void bootblock_fsp_temp_ram_init(void) {}
 /* Bootblock pre console init programing */
 void bootblock_cpu_init(void);
 void bootblock_pch_early_init(void);
-void bootblock_systemagent_early_init(void);
 void pch_uart_init(void);
 
 /* Bootblock post console init programing */
diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h
index e736d3b514..a6f7287f3a 100644
--- a/src/soc/intel/skylake/include/soc/iomap.h
+++ b/src/soc/intel/skylake/include/soc/iomap.h
@@ -58,6 +58,9 @@
 
 #define HECI1_BASE_ADDRESS	0xfed1a000
 
+/* CPU Trace reserved memory size */
+#define TRACE_MEMORY_SIZE	0x8000000	/* 128MiB */
+
 /*
  * I/O port address space
  */
diff --git a/src/soc/intel/skylake/include/soc/systemagent.h b/src/soc/intel/skylake/include/soc/systemagent.h
index c82f6913b2..c9b0bac5c7 100644
--- a/src/soc/intel/skylake/include/soc/systemagent.h
+++ b/src/soc/intel/skylake/include/soc/systemagent.h
@@ -15,9 +15,10 @@
  * GNU General Public License for more details.
  */
 
-#ifndef _SOC_SYSTEMAGENT_H_
-#define _SOC_SYSTEMAGENT_H_
+#ifndef SOC_SKYLAKE_SYSTEMAGENT_H
+#define SOC_SKYLAKE_SYSTEMAGENT_H
 
+#include <intelblocks/systemagent.h>
 #include <soc/iomap.h>
 
 #define SA_IGD_OPROM_VENDEV	0x80860406
@@ -44,7 +45,6 @@
 /* Device 0:0.0 PCI configuration space */
 
 #define EPBAR		0x40
-#define MCHBAR		0x48
 #define PCIEXBAR	0x60
 #define DMIBAR		0x68
 #define GGC		0x50	/* GMCH Graphics Control */
@@ -82,11 +82,6 @@
 #define REMAPBASE	0x90	/* Remap base. */
 #define REMAPLIMIT	0x98	/* Remap limit. */
 #define TOM		0xa0	/* Top of DRAM in memory controller space. */
-#define TOUUD		0xa8	/* Top of Upper Usable DRAM */
-#define BDSM		0xb0	/* Base Data Stolen Memory */
-#define BGSM		0xb4	/* Base GTT Stolen Memory */
-#define TSEG		0xb8	/* TSEG base */
-#define TOLUD		0xbc	/* Top of Low Used Memory */
 #define SKPAD		0xdc	/* Scratchpad Data */
 
 /* MCHBAR */
@@ -121,9 +116,6 @@
 /* Data is passed through bits 31:0 of the data register. */
 #define BIOS_MAILBOX_DATA			0x5da0
 
-/* CPU Trace reserved memory size */
-#define TRACE_MEMORY_SIZE	0x8000000	/* 128MiB */
-
 /* System Agent identification */
 u8 systemagent_revision(void);