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authorSubrata Banik <subratabanik@google.com>2023-10-16 14:06:27 +0530
committerSubrata Banik <subratabanik@google.com>2023-10-18 05:47:24 +0000
commit93ca15cc83ceb5f774a4ca9931cc7a3baea37bdb (patch)
tree328c5888648b764f0c2b118258b8a4df5cd98d86 /src
parent205f30bdfc8884966ff66c8d59d159e9325214c5 (diff)
soc/intel/{adl, mtl}: Avoid redundant display init by joining to MBUS
This patch ensures that the IGD joins the MBUS when the firmware splash screen feature is enabled (aka BMP_LOGO config is enabled). For ChromeOS platform, it prevents the i915 driver from reinitializing the display, which can save up to 75ms-80ms of boot time and eliminate a brief period of blank screen between the firmware splash screen and the OS login prompt. BUG=b:284799726 TEST=Able to build and boot google/rex. Change-Id: I36af167afa902053a987602d494a8830ad9b1b1a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/alderlake/Kconfig1
-rw-r--r--src/soc/intel/meteorlake/Kconfig1
2 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 1002f5a382..d70526b6bc 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -82,6 +82,7 @@ config SOC_INTEL_ALDERLAKE
select SOC_INTEL_COMMON_RESET
select SOC_INTEL_CSE_SEND_EOP_LATE if !BOARD_GOOGLE_BRYA_COMMON
select SOC_INTEL_CSE_SET_EOP
+ select SOC_INTEL_GFX_MBUS_JOIN if MAINBOARD_HAS_CHROMEOS && BMP_LOGO
select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
select HAVE_INTEL_COMPLIANCE_TEST_MODE
select SSE2
diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
index 590e8b80e1..b1a1cadf73 100644
--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
@@ -89,6 +89,7 @@ config SOC_INTEL_METEORLAKE
select SOC_INTEL_CSE_SEND_EOP_LATE if !MAINBOARD_HAS_CHROMEOS
select SOC_INTEL_CSE_SET_EOP
select SOC_INTEL_IOE_DIE_SUPPORT
+ select SOC_INTEL_GFX_MBUS_JOIN if MAINBOARD_HAS_CHROMEOS && BMP_LOGO
select SOC_INTEL_GFX_NON_PREFETCHABLE_MMIO
select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
select SSE2