diff options
| author | Wonkyu Kim <wonkyu.kim@intel.com> | 2022-04-26 16:36:21 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-04-28 12:56:04 +0000 |
| commit | 92c1042a35bf094e0bc5e93fb69e8c428ac3db7d (patch) | |
| tree | 7f21f631fdd7d26378e35c663624e0012e842f17 /src | |
| parent | be345c0bb48712bed1e653022cd2b9baae42a9c8 (diff) | |
soc/intel/cmn/sa: Introduce `PCIEXBAR_PCIEXBAREN` macro
Use PCIEXBAR_PCIEXBAREN instead of constant value(1)
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ica9e8162945da0a714822c37753914575c26024e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/common/block/systemagent/systemagent_early.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c index a77b307f5d..299f4c18a9 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_early.c +++ b/src/soc/intel/common/block/systemagent/systemagent_early.c @@ -69,13 +69,14 @@ void sa_set_pci_bar(const struct sa_mmio_descriptor *fixed_set_resources, base = pci_read_config32(SA_DEV_ROOT, index); /* If enabled don't program it. */ - if (base & 0x1) + if (base & PCIEXBAR_PCIEXBAREN) return; base = fixed_set_resources[i].base; if (base >> 32) pci_write_config32(SA_DEV_ROOT, index + 4, base >> 32); - pci_write_config32(SA_DEV_ROOT, index, (base & 0xffffffff) | 1); + pci_write_config32(SA_DEV_ROOT, index, + (base & 0xffffffff) | PCIEXBAR_PCIEXBAREN); } } @@ -97,7 +98,8 @@ void sa_set_mch_bar(const struct sa_mmio_descriptor *fixed_set_resources, index = fixed_set_resources[i].index; if (base >> 32) write32((void *)(uintptr_t)(MCH_BASE_ADDRESS + index + 4), base >> 32); - write32((void *)(uintptr_t)(MCH_BASE_ADDRESS + index), (base & 0xffffffff) | 1); + write32((void *)(uintptr_t)(MCH_BASE_ADDRESS + index), + (base & 0xffffffff) | PCIEXBAR_PCIEXBAREN); } } |