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authorKarthikeyan Ramasubramanian <kramasub@google.com>2021-03-12 12:17:40 -0700
committerKarthik Ramasubramanian <kramasub@google.com>2021-03-15 16:08:43 +0000
commit913824c910e8ba16832ec4faa07005ea820d9784 (patch)
tree727f0c3260bbbef1b739171f11fded71e8929ccc /src
parentab8961e7be8ec6da5ad2d0dcaf6402bef419c210 (diff)
mb/google/dedede/var/magolor: Fix DPTF passive and critical policies
Some of the temperature sensors defined in baseboard do not exist in magolor. With the format the DPTF policies are defined in magolor, all the entries from the baseboard are included and then the overrides applied. This causes the non-existent DPTF devices to be exported in the ACPI table and in turn OS reading invalid temperatures. Fix the format for DPTF passive and critical policies. BUG=None BRANCH=dedede TEST=Build and boot to OS in magolor. Ensure that the DPTF entries look correct in both static.c and SSDT tables i.e. passive and critical policies for applicable devices only are present. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I43f0b188e49e24657db055ce898ce159d499a22e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/dedede/variants/magolor/overridetree.cb16
1 files changed, 8 insertions, 8 deletions
diff --git a/src/mainboard/google/dedede/variants/magolor/overridetree.cb b/src/mainboard/google/dedede/variants/magolor/overridetree.cb
index 23932c3fd4..0deff6072a 100644
--- a/src/mainboard/google/dedede/variants/magolor/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/magolor/overridetree.cb
@@ -83,14 +83,14 @@ chip soc/intel/jasperlake
register "options.tsr[0].desc" = ""Memory""
register "options.tsr[1].desc" = ""Ambient""
- register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 90, 5000)"
- register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 6000)"
- register "policies.passive[2]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 60, 5000)"
-
- register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 105, SHUTDOWN)"
- register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 80, SHUTDOWN)"
- register "policies.critical[2]" = "DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN)"
-
+ register "policies.passive" = "{
+ [0] = DPTF_PASSIVE(CPU, CPU, 90, 5000),
+ [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 6000),
+ [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 60, 5000)}"
+ register "policies.critical" = "{
+ [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
+ [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 80, SHUTDOWN),
+ [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN)}"
register "controls.power_limits.pl1" = "{
.min_power = 3000,
.max_power = 7000,