diff options
| author | Subrata Banik <subratabanik@google.com> | 2023-03-07 16:34:22 +0000 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-05-25 05:03:32 +0000 |
| commit | 90a825a7bcb775827c5caa678794138e71df9930 (patch) | |
| tree | bec707a268e4b03e65234428b03f2637e601e205 /src | |
| parent | 04abc869ae32ab3f638620c6f7f1f49d738dacb9 (diff) | |
mb/google/rex: Enable SaGv
This patch overrides `SaGv` FSP-M UPD to enable SaGv feature to be
able to train memory (DIMM) at different frequencies.
On all latest Intel based platforms SaGv is expected to be enabled
to support dynamic switching of memory operating frequency.
BUG=b:267879107
TEST=Able to verify SaGv is enabled with 3 work point (0, 1 and 2)
and MRC retraining takes around ~20ms extra compared to SaGv being
disabled.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic680bfeab4dd285c0d3916ba5e917cc12bae3284
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73534
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb index 9a71e959c3..09d49d05a9 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb @@ -39,6 +39,8 @@ chip soc/intel/meteorlake # Enable CNVi BT register "cnvi_bt_core" = "true" + register "sagv" = "SAGV_ENABLED" + # Set on-board graphics as primary display register "skip_ext_gfx_scan" = "1" |