mb/google/brya/var/ghost: Enable NXP UWB SR150 chip

Add GPIO configuration and device tree to enable the chip.

BUG=b:240607130
BRANCH=firmware-brya-14505.B
TEST=Patch linux with NXP's pending drivers
     UWB device is probed and can respond to a simple hello packet

Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I83be712d243c365a5cbfe6f69a6bd85440c5bec7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

4 files changed, 25 insertions, 7 deletions

diff --git a/src/drivers/nxp/uwb/Makefile.inc b/src/drivers/nxp/uwb/Makefile.inc
index 11ba2736ab..9501a28c32 100644
--- a/src/drivers/nxp/uwb/Makefile.inc
+++ b/src/drivers/nxp/uwb/Makefile.inc
@@ -1 +1 @@
-ramstage-$(CONFIG_DRIVER_NXP_UWB_SR1XX) += uwb.c
+ramstage-$(CONFIG_DRIVERS_NXP_UWB_SR1XX) += uwb.c
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 2c27c71a57..9f124b38c4 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -67,6 +67,7 @@ config BOARD_GOOGLE_BASEBOARD_GHOST
 	select DRIVERS_I2C_CS42L42
 	select DRIVERS_I2C_MAX98396
 	select DRIVERS_INTEL_MIPI_CAMERA
+	select DRIVERS_NXP_UWB_SR1XX
 	select GBB_FLAG_DISABLE_LID_SHUTDOWN if VBOOT
 	select SOC_INTEL_COMMON_BLOCK_IPU
 
diff --git a/src/mainboard/google/brya/variants/ghost/gpio.c b/src/mainboard/google/brya/variants/ghost/gpio.c
index 73d6c7b025..1240803fb0 100644
--- a/src/mainboard/google/brya/variants/ghost/gpio.c
+++ b/src/mainboard/google/brya/variants/ghost/gpio.c
@@ -46,16 +46,16 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_A4 : GPP_A4 ==> ESPI_PCH_CS_EC_R_L configured on reset, do not touch */
 	/* GPP_A5 : GPP_A5 ==> ESPI_ALERT0 configured on reset, do not touch */
 	/* GPP_A6 : GPP_A6 ==> ESPI_ALERT1 configured on reset, do not touch */
-	/* GPP_A7 : No heuristic was found useful */
-	PAD_NC(GPP_A7, NONE),
+	/* GPP_A7 : PCH_UWB_WAKE */
+	PAD_CFG_GPO(GPP_A7, 0, DEEP),
 	/* GPP_A8 : HP_RST_ODL */
 	PAD_CFG_GPO(GPP_A8, 1, PLTRST),
 	/* GPP_A9 : GPP_A9 ==> ESPI_PCH_CLK_R configured on reset, do not touch */
 	/* GPP_A10 : GPP_A10 ==> ESPI_PCH_RST_EC_L configured on reset, do not touch */
 	/* GPP_A11 : [NF6: USB_C_GPP_A11] ==> EN_SPKR_PA */
 	PAD_CFG_GPO(GPP_A11, 1, DEEP),
-	/* GPP_A12 : No heuristic was found useful */
-	PAD_NC(GPP_A12, NONE),
+	/* GPP_A12 : EN_PP1800_UWB */
+	PAD_CFG_GPO(GPP_A12, 0, DEEP),
 	/* GPP_A13 : [NF6: USB_C_GPP_A13] ==> GSC_PCH_INT_ODL */
 	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
 	/* GPP_A14 : [NF1: USB_OC1# NF2: DDSP_HPD3 NF4: DISP_MISC3 NF6: USB_C_GPP_A14] ==> USB_C1_OC_ODL */
@@ -258,8 +258,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_F19, NONE, DEEP, NF6),
 	/* GPP_F20 : [] ==> UCAM_RST_L */
 	PAD_CFG_GPO(GPP_F20, 0, DEEP),
-	/* GPP_F21 : No heuristic was found useful */
-	PAD_NC(GPP_F21, NONE),
+	/* GPP_F21 : UWB_PCH_INT */
+	PAD_CFG_GPI_INT(GPP_F21, NONE, PLTRST, LEVEL),
 	/* GPP_F22 : No heuristic was found useful */
 	PAD_NC(GPP_F22, NONE),
 	/* GPP_F23 : No heuristic was found useful */
diff --git a/src/mainboard/google/brya/variants/ghost/overridetree.cb b/src/mainboard/google/brya/variants/ghost/overridetree.cb
index 211819fa22..95c1b4dba0 100644
--- a/src/mainboard/google/brya/variants/ghost/overridetree.cb
+++ b/src/mainboard/google/brya/variants/ghost/overridetree.cb
@@ -42,6 +42,12 @@ chip soc/intel/alderlake
 		[PchSerialIoIndexI2C7] = PchSerialIoDisabled,
 	}"
 
+	# GSPI config
+	register "serial_io_gspi_mode" = "{
+		[PchSerialIoIndexGSPI0] = PchSerialIoPci,
+		[PchSerialIoIndexGSPI1] = PchSerialIoPci,
+	}"
+
 	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"	# USB2_C0
 	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)"	# USB2_C1
 	register "usb2_ports[2]" = "USB2_PORT_EMPTY"
@@ -192,6 +198,17 @@ chip soc/intel/alderlake
 				device generic 0 on end
 			end
 		end
+		device ref gspi0 on
+			chip drivers/nxp/uwb
+				register "name" = ""UWB0""
+				register "desc" = ""NXP UWB Module""
+				register "speed" = "1000000"
+				register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_HIGH(GPP_F21)"
+				register "ce_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A12)"
+				register "ri_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A7)"
+				device spi 0 on end
+			end
+		end
 		device ref gspi1 on
 			chip drivers/spi/acpi
 				register "name" = ""CRFP""