diff options
| author | Casper Chang <casper_chang@wistron.corp-partner.google.com> | 2021-09-22 22:35:54 -0400 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-09-24 15:27:43 +0000 |
| commit | 8fcefd3f6f4991f3b6037f389e0252895a3ec03f (patch) | |
| tree | 9d26665fbe70cb4b8b4a6c117211e4c70a8ffdcc /src | |
| parent | 28e2945ab1ea5c4bfc5259442c29a76e17bc330d (diff) | |
soc/intel/alderlake: add MaxDramSpeed config
This change add MaxDramSpeed for variants usage to config dram speed.
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: Iba0fae0ab4ff0121dc63af792458492eeb21ec2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/alderlake/chip.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/romstage/fsp_params.c | 2 |
2 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 5f556c8e96..b9be02bf1d 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -436,6 +436,8 @@ struct soc_intel_alderlake_config { * 0 = VR_DOMAIN_IA Core 1 = VR_DOMAIN_GT. */ struct vr_config domain_vr_config[NUM_VR_DOMAINS]; + + uint16_t MaxDramSpeed; }; typedef struct soc_intel_alderlake_config config_t; diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 2d0f6daef4..698cff67ce 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -136,6 +136,8 @@ static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg, { m_cfg->SaGv = config->SaGv; m_cfg->RMT = config->RMT; + if (config->MaxDramSpeed) + m_cfg->DdrFreqLimit = config->MaxDramSpeed; } static void fill_fspm_cpu_params(FSP_M_CONFIG *m_cfg, |