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authorAntonello Dettori <dev@dettori.io>2016-09-01 16:50:42 +0200
committerMartin Roth <martinroth@google.com>2016-09-13 17:23:50 +0200
commit8d7181ddd16c06e484c74b0df4431e5557631b07 (patch)
tree4447a35889a4802b47b08359681505340479d440 /src
parent5ea2cadfff2055932a16339521be098dae510261 (diff)
southbridge/amd/agesa/hudson: transition away from device_t
Replace the use of the old device_t definition inside southbridge/amd/agesa/hudson. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: I39cd2afe5e2b6ee3963fd3e949eab1db9e986d71 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16401 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/southbridge/amd/agesa/hudson/early_setup.c4
-rw-r--r--src/southbridge/amd/agesa/hudson/hudson.h2
2 files changed, 3 insertions, 3 deletions
diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c
index 57119f910a..1cdaa056b8 100644
--- a/src/southbridge/amd/agesa/hudson/early_setup.c
+++ b/src/southbridge/amd/agesa/hudson/early_setup.c
@@ -28,7 +28,7 @@
void hudson_pci_port80(void)
{
u8 byte;
- device_t dev;
+ pci_devfn_t dev;
/* P2P Bridge */
dev = PCI_DEV(0, 0x14, 4);
@@ -73,7 +73,7 @@ void hudson_pci_port80(void)
void hudson_lpc_port80(void)
{
u8 byte;
- device_t dev;
+ pci_devfn_t dev;
/* Enable LPC controller */
outb(0xEC, 0xCD6);
diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h
index 92058c6791..d870845055 100644
--- a/src/southbridge/amd/agesa/hudson/hudson.h
+++ b/src/southbridge/amd/agesa/hudson/hudson.h
@@ -70,7 +70,7 @@ u8 pm_read8(u8 reg);
void pm_write16(u8 reg, u16 value);
u16 pm_read16(u16 reg);
-#ifdef __PRE_RAM__
+#ifdef __SIMPLE_DEVICE__
void hudson_lpc_port80(void);
void hudson_pci_port80(void);
void hudson_clk_output_48Mhz(void);