diff options
| author | Bora Guvendik <bora.guvendik@intel.corp-partner.google.com> | 2022-11-29 15:45:06 -0800 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2022-12-15 03:11:24 +0000 |
| commit | 8c46232005767ecbdebb7290f15cacf2756c9586 (patch) | |
| tree | 76d47f1d8ed1f249a81682447f900cbf076b134b /src | |
| parent | 447f5777aae39600af421b230d6ab22a18b96e84 (diff) | |
soc/intel/alderlake: Disable L1 substates for PCIe compliance test mode
Disable L1 substates for PCIe compliance test mode in order to get
continuous clock output.
BUG=b:235863379
TEST=Boot in compliance mode, check FSP settings
Signed-off-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Change-Id: I2a3b313425e00fe11f616d964f825baaef463c71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70165
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/alderlake/fsp_params.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 853b2f2c0d..224cf8a9ea 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -471,7 +471,9 @@ static const SI_PCH_DEVICE_INTERRUPT_CONFIG *pci_irq_to_fsp(size_t *out_count) */ static int get_l1_substate_control(enum L1_substates_control ctl) { - if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT)) + if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE)) + ctl = L1_SS_DISABLED; + else if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT)) ctl = L1_SS_L1_2; return ctl - 1; } |