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authorAngel Pons <th3fanbus@gmail.com>2021-03-03 16:55:01 +0100
committerPatrick Georgi <pgeorgi@google.com>2021-03-05 10:57:10 +0000
commit8af3e0eb426ddec222d20e1fd92600b5042ab3b4 (patch)
tree50af6f0de165d6ec0fa790d79d7fdcec25ee6935 /src
parentba7b90ecf216c8882d4b37579380e9a46d79e2f0 (diff)
soc/intel/broadwell/pch: Use Lynx Point smbus.c
Continue unifying Lynx Point and Wildcat Point (PCH for Broadwell) code. Define the WPT-LP SMBus PCI device ID, add it to smbus.c of Lynx Point, and drop all now-unnecessary SMBus code from Broadwell. Change-Id: I864d7c2dd47895a3c559e2f1219425cda9fd0c17 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/include/device/pci_ids.h1
-rw-r--r--src/soc/intel/broadwell/include/soc/smbus.h27
-rw-r--r--src/soc/intel/broadwell/pch/Makefile.inc2
-rw-r--r--src/soc/intel/broadwell/pch/early_pch.c1
-rw-r--r--src/soc/intel/broadwell/pch/smbus.c50
-rw-r--r--src/southbridge/intel/lynxpoint/smbus.c1
6 files changed, 3 insertions, 79 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index d99f307bd9..b54de0bdb2 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -3911,6 +3911,7 @@
/* Intel SMBUS device Ids */
#define PCI_DEVICE_ID_INTEL_LPT_H_SMBUS 0x8c22
#define PCI_DEVICE_ID_INTEL_LPT_LP_SMBUS 0x9c22
+#define PCI_DEVICE_ID_INTEL_WPT_LP_SMBUS 0x9ca2
#define PCI_DEVICE_ID_INTEL_APL_SMBUS 0x5ad4
#define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23
#define PCI_DEVICE_ID_INTEL_SPT_H_SMBUS 0xa123
diff --git a/src/soc/intel/broadwell/include/soc/smbus.h b/src/soc/intel/broadwell/include/soc/smbus.h
deleted file mode 100644
index 80d92ac932..0000000000
--- a/src/soc/intel/broadwell/include/soc/smbus.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _BROADWELL_SMBUS_H_
-#define _BROADWELL_SMBUS_H_
-
-/* PCI Configuration Space (D31:F3): SMBus */
-#define SMB_BASE 0x20
-#define HOSTC 0x40
-#define HST_EN (1 << 0)
-
-/* SMBus I/O bits. */
-#define SMBHSTSTAT 0x0
-#define SMBHSTCTL 0x2
-#define SMBHSTCMD 0x3
-#define SMBXMITADD 0x4
-#define SMBHSTDAT0 0x5
-#define SMBHSTDAT1 0x6
-#define SMBBLKDAT 0x7
-#define SMBTRNSADD 0x9
-#define SMBSLVDATA 0xa
-#define SMLINK_PIN_CTL 0xe
-#define SMBUS_PIN_CTL 0xf
-
-#define SMBUS_TIMEOUT (10 * 1000 * 100)
-#define SMBUS_SLAVE_ADDR 0x24
-
-#endif
diff --git a/src/soc/intel/broadwell/pch/Makefile.inc b/src/soc/intel/broadwell/pch/Makefile.inc
index 740c711198..42d8df1df4 100644
--- a/src/soc/intel/broadwell/pch/Makefile.inc
+++ b/src/soc/intel/broadwell/pch/Makefile.inc
@@ -26,7 +26,7 @@ romstage-y += power_state.c
ramstage-y += ramstage.c
ramstage-y += sata.c
ramstage-y += serialio.c
-ramstage-y += smbus.c
+ramstage-y += ../../../../southbridge/intel/lynxpoint/smbus.c
ramstage-y += smi.c
smm-y += smihandler.c
romstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c
diff --git a/src/soc/intel/broadwell/pch/early_pch.c b/src/soc/intel/broadwell/pch/early_pch.c
index 5e7ce2a6f8..cb45971772 100644
--- a/src/soc/intel/broadwell/pch/early_pch.c
+++ b/src/soc/intel/broadwell/pch/early_pch.c
@@ -11,7 +11,6 @@
#include <soc/pm.h>
#include <soc/rcba.h>
#include <soc/romstage.h>
-#include <soc/smbus.h>
#include <soc/intel/broadwell/pch/chip.h>
static void pch_route_interrupts(void)
diff --git a/src/soc/intel/broadwell/pch/smbus.c b/src/soc/intel/broadwell/pch/smbus.c
deleted file mode 100644
index bd57b0add4..0000000000
--- a/src/soc/intel/broadwell/pch/smbus.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/device.h>
-#include <device/path.h>
-#include <device/smbus.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <device/smbus_host.h>
-#include <southbridge/intel/common/smbus_ops.h>
-#include <soc/smbus.h>
-
-static void pch_smbus_init(struct device *dev)
-{
- struct resource *res;
- u16 reg16;
-
- /* Enable clock gating */
- /* FIXME: Using 32-bit ops with a 16-bit variable is a bug! These should be 16-bit! */
- reg16 = pci_read_config32(dev, 0x80);
- reg16 &= ~((1 << 8)|(1 << 10)|(1 << 12)|(1 << 14));
- pci_write_config32(dev, 0x80, reg16);
-
- /* Set Receive Slave Address */
- res = find_resource(dev, PCI_BASE_ADDRESS_4);
- if (res)
- smbus_set_slave_addr(res->base, SMBUS_SLAVE_ADDR);
-}
-
-static struct device_operations smbus_ops = {
- .read_resources = smbus_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .scan_bus = scan_smbus,
- .init = pch_smbus_init,
- .ops_smbus_bus = &lops_smbus_bus,
- .ops_pci = &pci_dev_ops_pci,
-};
-
-static const unsigned short pci_device_ids[] = {
- 0x9c22, /* LynxPoint */
- 0x9ca2, /* WildcatPoint */
- 0
-};
-
-static const struct pci_driver pch_smbus __pci_driver = {
- .ops = &smbus_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .devices = pci_device_ids,
-};
diff --git a/src/southbridge/intel/lynxpoint/smbus.c b/src/southbridge/intel/lynxpoint/smbus.c
index e2d42acb23..32c9c14e40 100644
--- a/src/southbridge/intel/lynxpoint/smbus.c
+++ b/src/southbridge/intel/lynxpoint/smbus.c
@@ -40,6 +40,7 @@ static struct device_operations smbus_ops = {
static const unsigned short pci_device_ids[] = {
PCI_DEVICE_ID_INTEL_LPT_H_SMBUS,
PCI_DEVICE_ID_INTEL_LPT_LP_SMBUS,
+ PCI_DEVICE_ID_INTEL_WPT_LP_SMBUS,
0
};