diff options
| author | Jonathan Zhang <jonzhang@fb.com> | 2020-08-10 14:01:25 -0700 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-08-13 11:40:39 +0000 |
| commit | 8aad2cafedea5de0211bd4b44dcfe78bd7eedc4b (patch) | |
| tree | 1a5f0bf31f65424f9a2aa45c74ad4cc288ea8548 /src | |
| parent | cd080999089243aa540b297a11b54cf5fa68db0b (diff) | |
soc/intel/xeon_sp/cpx: add CPUID for CPX-SP A1 processor
Add CPUID for CPX-SP A1 (also called QS) processor.
DeltaLake DVT server uses CPX-SP A1 processor.
TESTED=booted DeltaLake DVT server to target OS.
[root@localhost ~]# dmidecode -t 1
Getting SMBIOS data from sysfs.
SMBIOS 3.0 present.
Handle 0x0001, DMI type 1, 27 bytes
System Information
Manufacturer: Wiwynn
Product Name: Delta Lake DVT
Version: YoDL03
Serial Number: BZA02200122N01A
UUID: 000A0A22-2C29-1ED6-8259-000055DA2BFF
Wake-up Type: Reserved
SKU Number: Not Specified
Family: DeltaLake
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Ic8975f6bf752fd685b38b2d1f0a4da41983b57f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/cpu.c | 1 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/include/soc/cpu.h | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index cf903b872a..db9dd4b3bd 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -100,6 +100,7 @@ static struct device_operations cpu_dev_ops = { static const struct cpu_device_id cpu_table[] = { {X86_VENDOR_INTEL, CPUID_COOPERLAKE_SP_A0}, + {X86_VENDOR_INTEL, CPUID_COOPERLAKE_SP_A1}, {0, 0}, }; diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h index 14580004d0..3e740645ba 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h @@ -7,6 +7,7 @@ #include <cpu/x86/msr.h> #define CPUID_COOPERLAKE_SP_A0 0x05065a +#define CPUID_COOPERLAKE_SP_A1 0x05065b /* CPU bus clock is fixed at 100MHz */ #define CPU_BCLK 100 |