diff options
| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2022-10-07 11:27:56 +0200 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2022-10-12 13:17:24 +0000 |
| commit | 84dbace1ea49131d1647a8be994ed8d6776f03c5 (patch) | |
| tree | 8db14e59dd4c46c5ba45a518ea21f48ec5593a00 /src | |
| parent | d8fd2deda1e66acd0a6162bbea1d8d1ff524f055 (diff) | |
soc/intel/ehl: Fix incorrect access to MAC_MDIO_DATA register
Function 'setbits16' performs an 'OR' operation with the new data and
the origin register entry. This can lead to an incorrect value in the
register which can then lead to issues.
Change-Id: I0212420be770e2ffdabebbfaf5dfbf8d99d25915
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/elkhartlake/tsn_gbe.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/elkhartlake/tsn_gbe.c b/src/soc/intel/elkhartlake/tsn_gbe.c index 49ce4da95b..3e08897c5c 100644 --- a/src/soc/intel/elkhartlake/tsn_gbe.c +++ b/src/soc/intel/elkhartlake/tsn_gbe.c @@ -72,7 +72,7 @@ void tsn_mdio_write(void *base, uint8_t phy_adr, uint8_t reg_adr, uint16_t data) { enum cb_err status; - setbits16(base + TSN_MAC_MDIO_DATA, data); + write16(base + TSN_MAC_MDIO_DATA, data); clrsetbits32(base + TSN_MAC_MDIO_ADR, TSN_MAC_MDIO_ADR_MASK, TSN_MAC_PHYAD(phy_adr) | TSN_MAC_REGAD(reg_adr) | TSN_MAC_CLK_TRAIL_4 | TSN_MAC_CSR_CLK_DIV_62 |