diff options
| author | Taniya Das <tdas@codeaurora.org> | 2019-04-17 15:58:15 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-06-05 20:16:13 +0000 |
| commit | 846f8c0ced0c2b98c041b28159c2497e1275f1dc (patch) | |
| tree | 5ad933c0d39ab8dc7fd167b08593947d426ba9af /src | |
| parent | 1aac543a7af9e5353becc97853de8b4b1da7d4dd (diff) | |
coreboot: Add i2c clock API for qcs405
Add support of i2c clock enable, disable
and configure API.
Change-Id: Ia0b42357ac09bf0ab60aad18c44e5ef27fe9dac3
Signed-off-by: Shefali Jain <shefjain@codeaurora.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32545
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/qualcomm/qcs405/clock.c | 18 | ||||
| -rw-r--r-- | src/soc/qualcomm/qcs405/include/soc/clock.h | 7 |
2 files changed, 24 insertions, 1 deletions
diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c index 302652ba71..56824a430a 100644 --- a/src/soc/qualcomm/qcs405/clock.c +++ b/src/soc/qualcomm/qcs405/clock.c @@ -246,6 +246,14 @@ void clock_configure_spi(int blsp, int qup, uint32_t hz) clock_configure(spi_clk, spi_cfg, hz, ARRAY_SIZE(spi_cfg)); } +void clock_configure_i2c(uint32_t hz) +{ + struct qcs405_clock *i2c_clk = + (struct qcs405_clock *)&gcc->blsp1_qup1_i2c_clk; + + clock_configure(i2c_clk, i2c_cfg, hz, ARRAY_SIZE(i2c_cfg)); +} + void clock_enable_uart(void) { clock_enable(&gcc->blsp1_uart2_apps_cbcr); @@ -309,6 +317,16 @@ void clock_disable_spi(int blsp, int qup) } +void clock_enable_i2c(void) +{ + clock_enable(&gcc->blsp1_qup1_i2c_apps_cbcr); +} + +void clock_disable_i2c(void) +{ + clock_disable(&gcc->blsp1_qup1_i2c_apps_cbcr); +} + void clock_init(void) { clock_configure_gpll0(); diff --git a/src/soc/qualcomm/qcs405/include/soc/clock.h b/src/soc/qualcomm/qcs405/include/soc/clock.h index 8638128b15..55c1aaf7a8 100644 --- a/src/soc/qualcomm/qcs405/include/soc/clock.h +++ b/src/soc/qualcomm/qcs405/include/soc/clock.h @@ -69,7 +69,9 @@ struct qcs405_gcc { u8 _res1[0x2000 - 0x1014]; u32 blsp1_qup1_bcr; u32 blsp1_qup1_spi_apps_cbcr; - u8 _res2[0x2024 - 0x2008]; + u32 blsp1_qup1_i2c_apps_cbcr; + struct qcs405_clock blsp1_qup1_i2c_clk; + u8 _res2[0x2024 - 0x2020]; struct qcs405_clock blsp1_qup1_spi_clk; u8 _res3[0x3008-0x2038]; u32 blsp1_qup2_bcr; @@ -179,10 +181,13 @@ void clock_reset_aop(void); int clock_configure_qspi(uint32_t hz); int clock_reset_bcr(void *bcr_addr, bool reset); void clock_configure_uart(uint32_t hz); +void clock_configure_i2c(uint32_t hz); void clock_configure_spi(int blsp, int qup, uint32_t hz); void clock_enable_uart(void); void clock_disable_uart(void); void clock_enable_spi(int blsp, int qup); void clock_disable_spi(int blsp, int qup); +void clock_enable_i2c(void); +void clock_disable_i2c(void); #endif // __SOC_QUALCOMM_QCS405_CLOCK_H__ |