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authorTim Wawrzynczak <twawrzynczak@chromium.org>2022-08-16 14:41:33 -0600
committerTim Wawrzynczak <twawrzynczak@chromium.org>2022-08-30 15:17:16 +0000
commit8392a299ff053ff28e971ad510217909acd3f9d2 (patch)
treeb99c3ebc72ffb90a5fbf90c2d31b23cf2791d2f3 /src
parent9ebfb8d4130c8b61015b6bcdf477216bab7e3086 (diff)
soc/intel/cmn/block/acpi: Modify GPIO Methods to use bitfields
IMHO, using bitfields directly in the Field declaration makes the ASL code more readable then directly manipulating the entire 32-bit dword. TEST=ACPI code using several of these Methods still works (google/agah dGPU ACPI code) Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I9909700022d8b55db3f5208010bdff11ddaf4e7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/66812 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/common/block/acpi/acpi/gpio_op.asl44
1 files changed, 18 insertions, 26 deletions
diff --git a/src/soc/intel/common/block/acpi/acpi/gpio_op.asl b/src/soc/intel/common/block/acpi/acpi/gpio_op.asl
index 9fa3dc4a86..55d254057a 100644
--- a/src/soc/intel/common/block/acpi/acpi/gpio_op.asl
+++ b/src/soc/intel/common/block/acpi/acpi/gpio_op.asl
@@ -10,11 +10,11 @@ Method (GRXS, 1, Serialized)
OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
Field (PREG, AnyAcc, NoLock, Preserve)
{
- VAL0, 32
+ , 1,
+ RXST, 1,
}
- Local0 = (PAD_CFG0_RX_STATE & VAL0) >> PAD_CFG0_RX_STATE_BIT
- Return (Local0)
+ Return (RXST)
}
/*
@@ -26,11 +26,10 @@ Method (GTXS, 1, Serialized)
OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
Field (PREG, AnyAcc, NoLock, Preserve)
{
- VAL0, 32
+ TXST, 1,
}
- Local0 = PAD_CFG0_TX_STATE & VAL0
- Return (Local0)
+ Return (TXST)
}
/*
@@ -42,9 +41,9 @@ Method (STXS, 1, Serialized)
OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
Field (PREG, AnyAcc, NoLock, Preserve)
{
- VAL0, 32
+ TXST, 1,
}
- VAL0 |= PAD_CFG0_TX_STATE
+ TXST = 1
}
/*
@@ -56,9 +55,9 @@ Method (CTXS, 1, Serialized)
OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
Field (PREG, AnyAcc, NoLock, Preserve)
{
- VAL0, 32
+ TXST, 1,
}
- VAL0 &= ~PAD_CFG0_TX_STATE
+ TXST = 0
}
/*
@@ -75,11 +74,10 @@ Method (GPMO, 2, Serialized)
OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
Field (PREG, AnyAcc, NoLock, Preserve)
{
- VAL0, 32
+ , 10,
+ MODE, 3,
}
- Local0 = ~PAD_CFG0_MODE_MASK & VAL0
- Arg1 = (Arg1 << PAD_CFG0_MODE_SHIFT) & PAD_CFG0_MODE_MASK
- VAL0 = Local0 | Arg1
+ MODE = Arg1
}
/*
@@ -94,14 +92,11 @@ Method (GTXE, 2, Serialized)
OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
Field (PREG, AnyAcc, NoLock, Preserve)
{
- VAL0, 32
+ , 8,
+ TXDI, 1,
}
- If (Arg1 == 1) {
- VAL0 &= ~PAD_CFG0_TX_DISABLE
- } ElseIf (Arg1 == 0){
- VAL0 |= PAD_CFG0_TX_DISABLE
- }
+ TXDI = !Arg1
}
/*
@@ -116,12 +111,9 @@ Method (GRXE, 2, Serialized)
OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
Field (PREG, AnyAcc, NoLock, Preserve)
{
- VAL0, 32
+ , 9,
+ RXDI, 1,
}
- If (Arg1 == 1) {
- VAL0 &= ~PAD_CFG0_RX_DISABLE
- } ElseIf (Arg1 == 0){
- VAL0 |= PAD_CFG0_RX_DISABLE
- }
+ RXDI = !Arg1
}