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authorSean Rhodes <sean@starlabs.systems>2024-08-12 10:04:22 +0100
committerSean Rhodes <sean@starlabs.systems>2024-10-11 11:27:04 +0000
commit7f66fa4299ff5f64c94093a2a19b688dd5e80078 (patch)
treeda83323bfdd10e6e4eaaec92bf9be02a956610b4 /src
parentdd5ff243113996b0648f52e6d0cfe7bbb41c781e (diff)
mb/starlabs/starlite_adl: Alphabetize and group FSP UPDs
Change-Id: Ibe47f242ce12fc4906baeee89393a34a56eaca76 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83881 Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb10
1 files changed, 4 insertions, 6 deletions
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
index a302e4f1c4..fc21f18d74 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
@@ -8,13 +8,11 @@ chip soc/intel/alderlake
},
}"
- # FSP Memory
- register "sagv" = "SaGv_Enabled"
-
- # FSP Silicon
- register "eist_enable" = "true"
- register "cnvi_bt_core" = "true"
+ # FSP UPDs
register "cnvi_bt_audio_offload" = "true"
+ register "cnvi_bt_core" = "true"
+ register "eist_enable" = "true"
+ register "sagv" = "SaGv_Enabled"
# Serial I/O
register "serial_io_i2c_mode" = "{