diff options
| author | Furquan Shaikh <furquan@google.com> | 2020-11-30 15:46:33 -0800 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-12-08 22:58:38 +0000 |
| commit | 797b1cc9cf71676d09856b47c8f8789beb3eb94c (patch) | |
| tree | a6dc7f3857aaff412828e52711f14811bb8c8754 /src | |
| parent | 68ca21ae3dfb4d22b15b0be8b6e337eb9949471a (diff) | |
mb/google/deltaur: Restrict RW_DIAG to lower 16MiB
This change restricts RW_DIAG region to lower 16MiB to ensure that the
extended BIOS checker for FMAP does not complain about 16MiB boundary
crossing.
I haven't updated any other regions to occupy the newly freed space
but it is fine since this board is dead and should be dropped from
coreboot soon.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I19ab204fbe3e020e42baf68bfa350dcff32066a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/deltaur/chromeos-gbe.fmd | 6 | ||||
| -rw-r--r-- | src/mainboard/google/deltaur/chromeos.fmd | 6 |
2 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/google/deltaur/chromeos-gbe.fmd b/src/mainboard/google/deltaur/chromeos-gbe.fmd index 9b6fec3ab2..91918e88b9 100644 --- a/src/mainboard/google/deltaur/chromeos-gbe.fmd +++ b/src/mainboard/google/deltaur/chromeos-gbe.fmd @@ -7,9 +7,9 @@ FLASH@0xfe000000 0x2000000 { SI_PDR(PRESERVE)@0x602000 0x4000 } SI_BIOS@0x606000 0x19fa000 { - RW_DIAG@0x0 0x10ca000 { - RW_LEGACY(CBFS)@0x0 0x10ba000 - DIAG_NVRAM@0x10ba000 0x10000 + RW_DIAG@0x0 0x9fa000 { + RW_LEGACY(CBFS)@0x0 0x9ea000 + DIAG_NVRAM@0x9ea000 0x10000 } RW_SECTION_A@0x10ca000 0x280000 { VBLOCK_A@0x0 0x10000 diff --git a/src/mainboard/google/deltaur/chromeos.fmd b/src/mainboard/google/deltaur/chromeos.fmd index bbec112b78..a84a448999 100644 --- a/src/mainboard/google/deltaur/chromeos.fmd +++ b/src/mainboard/google/deltaur/chromeos.fmd @@ -6,9 +6,9 @@ FLASH@0xfe000000 0x2000000 { SI_PDR(PRESERVE)@0x602000 0x4000 } SI_BIOS@0x606000 0x19fa000 { - RW_DIAG@0x0 0x10ca000 { - RW_LEGACY(CBFS)@0x0 0x10ba000 - DIAG_NVRAM@0x10ba000 0x10000 + RW_DIAG@0x0 0x9fa000 { + RW_LEGACY(CBFS)@0x0 0x9ea000 + DIAG_NVRAM@0x9ea000 0x10000 } RW_SECTION_A@0x10ca000 0x280000 { VBLOCK_A@0x0 0x10000 |