diff options
| author | Subrata Banik <subratabanik@google.com> | 2024-11-04 14:16:30 +0000 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-11-12 03:16:43 +0000 |
| commit | 762b6a9639135d61f12dc276931e2c11540eb9b1 (patch) | |
| tree | 02384fcf922859e638b13f3f5055291d35d02428 /src | |
| parent | 28f71b5c3adf2bf82f55b359f26a58a78b0f172e (diff) | |
soc/intel/alderlake: Optimize reset handling for non-UFS boot
This patch optimizes the reset handling in the Alder Lake romstage while
disabling the UFS controller in an uni-boot scenario (a unified AP
firmware image can boot both UFS and non-UFS systems).
It introduces a check in `mainboard_expects_another_reset()` to skip
unnecessary resets when a CSE slot switch is due, meaning CSE is not
booting from the RW slot. This saves one reset for non-UFS SKUs when
a CSE slot switch is pending.
The patch also relocates the `cse_fw_sync()` call after disabling the
UFS controllers to ensure the system reset flow can be better optimized
and combined with any expected resets due to CSE synchronization.
TEST=Able to build google/trulo eMMC sku and able to save one reset.
Without this patch:
1. Warm reset after disabling UFS (1st reset)
2. Global reset after CSE sync (2nd reset)
3. Warm reset after disabling UFS (3rd reset)
4. Boot to OS
With this patch:
1. Skip disabling UFS if CSE sync is due, aka no reset.
2. Global reset after CSE sync (1st reset)
3. CSE is booting from slot RW meaning CSE sync is done, perform UFS
disabling and issue a warm reset after disabling UFS (2nd reset)
4. Boot to OS
Change-Id: I04e6943fb136d126a1d1a829aadb316d2cdd0ac9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/alderlake/romstage/romstage.c | 20 |
1 files changed, 16 insertions, 4 deletions
diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index 3acd2fd7c3..d2abaee532 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -34,7 +34,19 @@ bool __weak mainboard_expects_another_reset(void) { - return false; + bool reset_pending = true; + + if (!CONFIG(SOC_INTEL_CSE_LITE_SKU)) + reset_pending = false; + + /* + * Skip reset if CSE slot switch is pending meaning, CSE is booting from RO. + * CSE state switch will issue a reset anyway. + */ + if (is_cse_boot_to_rw() == true) + reset_pending = false; + + return reset_pending; } static void disable_ufs(void) @@ -182,9 +194,6 @@ void mainboard_romstage_entry(void) if (!CONFIG(INTEL_TXT)) disable_intel_txt(); - if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE) && !s3wake) - cse_fw_sync(); - /* Program to Disable UFS Controllers */ if (!is_devfn_enabled(PCH_DEVFN_UFS) && (CONFIG(USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS))) { @@ -196,6 +205,9 @@ void mainboard_romstage_entry(void) } } + if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE) && !s3wake) + cse_fw_sync(); + /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ systemagent_early_init(); /* Program SMBus base address and enable it */ |