diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2020-10-10 16:37:44 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-10-14 14:49:09 +0000 |
| commit | 7223bfa47ea831fca634550ad7e7a534d0fe8ec9 (patch) | |
| tree | 4cf54322a32d8d5164587cf7ebeb10a5d11d1492 /src | |
| parent | 9b4f221026d16cc4b6dc0eadad074ef44ff1ffed (diff) | |
mb/intel/adlrvp: Add ADL-P mainboard ASL code
Add required ASL files into dsdt.asl
TEST=Dump and disassemble DSDT and verify all ACPI devices are present.
Change-Id: I70829e2bdb12fad20627d9aea47e745d9095f07a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/intel/adlrvp/dsdt.asl | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/src/mainboard/intel/adlrvp/dsdt.asl b/src/mainboard/intel/adlrvp/dsdt.asl index 6163d01d3c..d4fb7a4273 100644 --- a/src/mainboard/intel/adlrvp/dsdt.asl +++ b/src/mainboard/intel/adlrvp/dsdt.asl @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <baseboard/ec.h> +#include <baseboard/gpio.h> DefinitionBlock( "dsdt.aml", @@ -11,5 +13,35 @@ DefinitionBlock( 0x20110725 /* OEM revision */ ) { + #include <soc/intel/common/block/acpi/acpi/platform.asl> + /* global NVS and variables */ + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + + #include <cpu/intel/common/acpi/cpu.asl> + + Device (\_SB.PCI0) { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/alderlake/acpi/southbridge.asl> + #include <soc/intel/alderlake/acpi/tcss.asl> + #include <soc/intel/common/block/acpi/acpi/ipu.asl> + } + +#if CONFIG(CHROMEOS) + /* Chrome OS specific */ + #include <vendorcode/google/chromeos/acpi/chromeos.asl> +#endif + +#if CONFIG(EC_GOOGLE_CHROMEEC) + /* Chrome OS Embedded Controller */ + Scope (\_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include <ec/google/chromeec/acpi/superio.asl> + /* ACPI code for EC functions */ + #include <ec/google/chromeec/acpi/ec.asl> + } +#endif + + #include <southbridge/intel/common/acpi/sleepstates.asl> } |