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authorDavid Wu <david_wu@quanta.corp-partner.google.com>2020-12-29 19:02:59 +0800
committerTim Wawrzynczak <twawrzynczak@chromium.org>2021-01-06 18:31:55 +0000
commit6df0c67c090d8f4243af5cb827b4567f5e2df99e (patch)
tree71f948c60eeda33821574c494ab4726adce605aa /src
parent3b55a8d676697de7be3cbff08f538aa6f37cdce6 (diff)
mb/google/volteer/var/voema: Update Aux settings for Port 0
On Voema port 0 (MB PORT) does not have a retimer so the port needs to be configured for the SOC to handle Aux orientation flipping. BUG=b:176462544 TEST=tested on voema Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I3d31a5b848f56126f8ffe2babb29085471e8224f Reviewed-on: https://review.coreboot.org/c/coreboot/+/48976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/volteer/variants/voema/overridetree.cb6
1 files changed, 4 insertions, 2 deletions
diff --git a/src/mainboard/google/volteer/variants/voema/overridetree.cb b/src/mainboard/google/volteer/variants/voema/overridetree.cb
index daea4327b8..ff6b64bfac 100644
--- a/src/mainboard/google/volteer/variants/voema/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/voema/overridetree.cb
@@ -5,6 +5,10 @@ chip soc/intel/tigerlake
# and controller 1 channel 0 and 1.
register "CmdMirror" = "0x00000033"
+ register "TcssAuxOri" = "1"
+ register "IomTypeCPortPadCfg[0]" = "0x090E000A"
+ register "IomTypeCPortPadCfg[1]" = "0x090E000D"
+
# Disable WLAN PCIE 7
register "PcieRpEnable[6]" = "0"
register "PcieRpLtrEnable[6]" = "0"
@@ -105,8 +109,6 @@ chip soc/intel/tigerlake
chip drivers/intel/pmc_mux/conn
register "usb2_port_number" = "5"
register "usb3_port_number" = "1"
- # SBU is fixed, HSL follows CC
- register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
device generic 0 alias conn0 on end
end
chip drivers/intel/pmc_mux/conn