diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-10-05 18:30:58 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-10-09 21:30:46 +0200 |
| commit | 6bc3b9683108abd13c9108cc976cc81a9a2d1ddc (patch) | |
| tree | 6f4d175e5d37f51f8bfa599d0ac4efd6f06f7211 /src | |
| parent | 59840d1dee3762a0cb2745429ed57b343a48d357 (diff) | |
northbridge/amd/amdmct/mct_ddr3: Remove commented code
Change-Id: I2a52db28353f8575d11218af936b4a233fd05f77
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16889
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 16 | ||||
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 17 |
2 files changed, 0 insertions, 33 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index bd26a6fc45..f3fba25ca1 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -34,8 +34,6 @@ #include <reset.h> -// #define DEBUG_DIMM_SPD 1 - static u8 ReconfigureDIMMspare_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); static void DQSTiming_D(struct MCTStatStruc *pMCTstat, @@ -2829,17 +2827,6 @@ restartinit: * speed is the same as the speed used in the previous boot. * How to get the desired speed at this point in the code? */ -#if 0 - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - struct DCTStatStruc *pDCTstat; - pDCTstat = pDCTstatA + Node; - - if (pDCTstat->NodePresent) { - if (pDCTstat->spd_data.nvram_memclk[0] != pDCTstat->DIMMAutoSpeed) - allow_config_restore = 0; - } - } -#endif printk(BIOS_DEBUG, "mctAutoInitMCT_D: DQSTiming_D\n"); DQSTiming_D(pMCTstat, pDCTstatA, allow_config_restore); /* Get Receiver Enable and DQS signal timing*/ @@ -3623,7 +3610,6 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat, } retry_dqs_training_and_levelization: - // nv_DQSTrainCTL = mctGet_NVbits(NV_DQSTrainCTL); nv_DQSTrainCTL = !allow_config_restore; mct_BeforeDQSTrain_D(pMCTstat, pDCTstatA); @@ -3662,8 +3648,6 @@ retry_dqs_training_and_levelization: mct_WriteLevelization_HW(pMCTstat, pDCTstatA, SecondPass); if (is_fam15h()) { - /* Receiver Enable Training Pass 2 */ - // TrainReceiverEn_D(pMCTstat, pDCTstatA, SecondPass); /* TODO: * Determine why running TrainReceiverEn_D in SecondPass diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index eac201346d..8c134c322b 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -951,11 +951,6 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, * This does not seem to be needed, and has a tendency to lock up the * boot process while attempting to write the test pattern. */ -#if 0 - SetUpperFSbase(TestAddr0); - WriteLNTestPattern(TestAddr0 << 8, (uint8_t *)TestPattern2_D, 1); - mct_Read1LTestPattern_D(pMCTstat, pDCTstat, TestAddr0); -#endif } MaxDelay_CH[Channel] = CTLRMaxDelay; } @@ -1087,7 +1082,6 @@ static void generate_dram_receiver_enable_training_pattern_fam15(struct MCTStatS /* 2.10.5.8.6.1.2 */ dword = Get_NB32_DCT(dev, dct, 0x270); dword &= ~(0x7ffff); /* DataPrbsSeed = 55555 */ -// dword |= (0x55555); dword |= (0x44443); /* Use AGESA seed */ Set_NB32_DCT(dev, dct, 0x270, dword); @@ -1097,17 +1091,6 @@ static void generate_dram_receiver_enable_training_pattern_fam15(struct MCTStatS dword |= 192; Set_NB32_DCT(dev, dct, 0x260, dword); -#if 0 - /* TODO: This applies to Fam15h model 10h and above only */ - /* Program Bubble Count and CmdStreamLen */ - dword = Get_NB32_DCT(dev, dct, 0x25c); - dword &= ~(0x3ff << 12); /* BubbleCnt = 0 */ - dword &= ~(0x3ff << 22); /* BubbleCnt2 = 0 */ - dword &= ~(0xff); /* CmdStreamLen = 1 */ - dword |= 0x1; - Set_NB32_DCT(dev, dct, 0x25c, dword); -#endif - /* Configure Target A */ dword = Get_NB32_DCT(dev, dct, 0x254); dword &= ~(0x7 << 24); /* TgtChipSelect = Receiver */ |