diff options
| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2023-12-21 07:08:49 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-01-04 14:20:06 +0000 |
| commit | 68642ca981b0976f5d2f4a118ffc669ff0d2d660 (patch) | |
| tree | 7de14b1ec4f126c132ce5109205ac3eff5dc4fc4 /src | |
| parent | 41a5954a6785bfad95dce36611b92f1123e350e2 (diff) | |
nb/intel/sandybridge/raminit: Honor SPD's dll_off_mode
In DDR3 DLL-Off mode is an optional feature advertised by SPD.
Honor the SPD and only use DLL-Off mode when all DIMMs on the
same channel indicate support for it.
The same is done on MRC.bin.
Tested on Lenovo X220: Still boots fine.
Change-Id: Ief4bfb9e045cad7ff9953f6fda248586ea951a52
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79758
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_common.c | 22 |
1 files changed, 14 insertions, 8 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index c2a30515fb..2e4967532e 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -667,26 +667,32 @@ static void write_mrreg(ramctr_timing *ctrl, int channel, int slotrank, int reg, } /* Obtain optimal power down mode for current configuration */ -static enum power_down_mode get_power_down_mode(ramctr_timing *ctrl) +static enum power_down_mode get_power_down_mode(ramctr_timing *ctrl, int channel) { + int slotrank; + if (ctrl->tXP > 8) return PDM_NONE; if (ctrl->tXPDLL > 32) return PDM_PPD; + FOR_ALL_POPULATED_RANKS + if (!ctrl->info.dimm[channel][slotrank >> 1].flags.dll_off_mode) + return PDM_APD_PPD; + if (CONFIG(RAMINIT_ALWAYS_ALLOW_DLL_OFF) || get_platform_type() == PLATFORM_MOBILE) return PDM_DLL_OFF; return PDM_APD_PPD; } -static u32 make_mr0(ramctr_timing *ctrl, u8 rank) +static u32 make_mr0(ramctr_timing *ctrl, int channel, u8 rank) { u16 mr0reg, mch_cas, mch_wr; static const u8 mch_wr_t[12] = { 1, 2, 3, 4, 0, 5, 0, 6, 0, 7, 0, 0 }; - const enum power_down_mode power_down = get_power_down_mode(ctrl); + const enum power_down_mode power_down = get_power_down_mode(ctrl, channel); const bool slow_exit = power_down == PDM_DLL_OFF || power_down == PDM_APD_DLL_OFF; @@ -715,7 +721,7 @@ static u32 make_mr0(ramctr_timing *ctrl, u8 rank) static void dram_mr0(ramctr_timing *ctrl, u8 rank, int channel) { - write_mrreg(ctrl, channel, rank, 0, make_mr0(ctrl, rank)); + write_mrreg(ctrl, channel, rank, 0, make_mr0(ctrl, channel, rank)); } static odtmap get_ODT(ramctr_timing *ctrl, int channel) @@ -2818,13 +2824,13 @@ void final_registers(ramctr_timing *ctrl) }; tc_othp.tCPDED = 1; mchbar_write32(TC_OTHP_ch(channel), tc_othp.raw); - } - /* 64 DCLKs until idle, decision per rank */ - mchbar_write32(PM_PDWN_CONFIG, get_power_down_mode(ctrl) << 8 | 64); + /* 64 DCLKs until idle, decision per rank */ + r32 = get_power_down_mode(ctrl, channel) << 8 | 64; + mchbar_write32(PM_PDWN_CONFIG_ch(channel), r32); - FOR_ALL_CHANNELS mchbar_write32(PM_TRML_M_CONFIG_ch(channel), 0x00000aaa); + } mchbar_write32(PM_BW_LIMIT_CONFIG, 0x5f7003ff); mchbar_write32(PM_DLL_CONFIG, 0x00073000 | ctrl->mdll_wake_delay); |