diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-06-04 12:54:00 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-06-07 11:37:01 +0000 |
| commit | 685dc56b9f2cf639c8aa72eed948e02044683642 (patch) | |
| tree | 194a00f4ef36c32f61a653c9cec3294eb176ec8d /src | |
| parent | 772c09739ea81e589c42bd8e063119a5fdf38176 (diff) | |
sb/intel/ibexpeak: Drop P_LVLx support in FADT
IO MWAIT redirection is not enabled. The code is missing, but C-states
should instead be reported using the _CST ACPI object.
Change-Id: I21fd2fa6ee4aa1ed57694549d5cb48159f37af26
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/lenovo/t410/devicetree.cb | 1 | ||||
| -rw-r--r-- | src/mainboard/lenovo/x201/devicetree.cb | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/ibexpeak/fadt.c | 13 |
3 files changed, 3 insertions, 12 deletions
diff --git a/src/mainboard/lenovo/t410/devicetree.cb b/src/mainboard/lenovo/t410/devicetree.cb index a4f3463268..e3456f2bdf 100644 --- a/src/mainboard/lenovo/t410/devicetree.cb +++ b/src/mainboard/lenovo/t410/devicetree.cb @@ -49,7 +49,6 @@ chip northbridge/intel/ironlake register "gen3_dec" = "0x1c1681" # EC ? register "gen4_dec" = "0x040069" # ? - register "c2_latency" = "1" register "docking_supported" = "1" register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index e142a1c692..effe4ef261 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -49,7 +49,6 @@ chip northbridge/intel/ironlake register "gen3_dec" = "0x1c1681" register "gen4_dec" = "0x040069" - register "c2_latency" = "1" register "docking_supported" = "1" register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" diff --git a/src/southbridge/intel/ibexpeak/fadt.c b/src/southbridge/intel/ibexpeak/fadt.c index ccd9f57b74..40c8bdc57b 100644 --- a/src/southbridge/intel/ibexpeak/fadt.c +++ b/src/southbridge/intel/ibexpeak/fadt.c @@ -11,7 +11,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) struct device *dev = pcidev_on_root(0x1f, 0); struct southbridge_intel_ibexpeak_config *chip = dev->chip_info; u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; - int c2_latency; fadt->sci_int = 0x9; @@ -32,12 +31,9 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->pm2_cnt_len = 1; fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 16; - c2_latency = chip->c2_latency; - if (!c2_latency) { - c2_latency = 101; /* c2 unsupported */ - } - fadt->p_lvl2_lat = c2_latency; - fadt->p_lvl3_lat = 87; + /* P_LVLx not used */ + fadt->p_lvl2_lat = 101; + fadt->p_lvl3_lat = 1001; /* P_CNT not supported */ fadt->duty_offset = 0; fadt->duty_width = 0; @@ -54,9 +50,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) if (chip->docking_supported) { fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; } - if (c2_latency < 100) { - fadt->flags |= ACPI_FADT_C2_MP_SUPPORTED; - } fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = 32; |