diff options
| author | Simon Zhou <zhouguohui@huaqin.corp-partner.google.com> | 2023-05-17 10:12:29 +0800 |
|---|---|---|
| committer | Jakub Czapiga <jacz@semihalf.com> | 2023-05-22 07:24:55 +0000 |
| commit | 6477d19e6434b6a84eb908fea77f7c7d27ca5e1e (patch) | |
| tree | 5a3f7077c5a6a56a23c204b335eeb6b22861da31 /src | |
| parent | 4e4141ac6c38a5982adf2248211e3f6a356554c7 (diff) | |
mb/google/rex/var/screebo: enable fingerprint
BUG=b:278156430
TEST=verify the fingerprint on screebo
Change-Id: I986e470b28145f7b17427e794055929a4283c721
Signed-off-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75287
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dolan Liu <liuyong5@huaqin.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/rex/variants/screebo/gpio.c | 2 | ||||
| -rw-r--r-- | src/mainboard/google/rex/variants/screebo/overridetree.cb | 15 |
2 files changed, 16 insertions, 1 deletions
diff --git a/src/mainboard/google/rex/variants/screebo/gpio.c b/src/mainboard/google/rex/variants/screebo/gpio.c index 7f5f72fa6f..f31506c1b6 100644 --- a/src/mainboard/google/rex/variants/screebo/gpio.c +++ b/src/mainboard/google/rex/variants/screebo/gpio.c @@ -398,7 +398,7 @@ static const struct pad_config romstage_gpio_table[] = { PAD_CFG_GPO(GPP_B08, 0, DEEP), /* A20 : [] ==> SSD_PERST_L */ PAD_CFG_GPO(GPP_A20, 0, DEEP), - /* GPP_C23 : [] ==> FP_RST_ODL */ + /* GPP_C21 : [] ==> FP_RST_ODL */ PAD_CFG_GPO(GPP_C21, 0, DEEP), /* GPP_D02 : [] ==> SD_PERST_L */ PAD_CFG_GPO(GPP_D02, 1, DEEP), diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb index 9e3f9f6511..2e7b208329 100644 --- a/src/mainboard/google/rex/variants/screebo/overridetree.cb +++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb @@ -319,6 +319,21 @@ chip soc/intel/meteorlake device i2c 50 on end end end + device ref gspi1 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E10_IRQ)" + register "wake" = "GPE0_DW1_10" + register "has_power_resource" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C21)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B08)" + register "enable_delay_ms" = "3" + device spi 0 on end + end # FPMCU + end device ref soc_espi on chip ec/google/chromeec use conn0 as mux_conn[0] |