diff options
| author | Matt DeVillier <matt.devillier@puri.sm> | 2021-03-19 11:51:27 -0500 |
|---|---|---|
| committer | Matt DeVillier <matt.devillier@gmail.com> | 2021-03-24 20:31:08 +0000 |
| commit | 640f549eacc365745acd32e78340c225b496af52 (patch) | |
| tree | c84b0b6a27b98cd64f72de72d1660f5d26494ecc /src | |
| parent | 156be2db5ac09f9daa5c7843bfecfad4902e99a8 (diff) | |
mb/purism/librem_mini: Drop superfluous devices from devicetree
The 'device pci 00.0 on end' entries are not necessary for socketed
devices unless a chip driver needs to be bound to a device, so remove
them from the devicetree. Also remove the `drivers/wifi/generic` chip
driver as it was not necessary either.
Change-Id: Id5f2e34d98b236f9cfac9f0afd8a8017e349603f
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb index 8fb84ce581..69d1b423bd 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb @@ -187,10 +187,7 @@ chip soc/intel/cannonlake device pci 1c.4 off end # PCI Express Port 5 device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 on # PCI Express Port 8 - chip drivers/wifi/generic - device pci 00.0 on end # x1 M.2/E 2230 (WLAN) - end + device pci 1c.7 on # PCI Express Port 8 -- x1 M.2/E 2230 (WLAN) register "PcieRpSlotImplemented[7]" = "1" register "PcieRpEnable[7]" = "1" register "PcieRpLtrEnable[7]" = "1" @@ -207,8 +204,7 @@ chip soc/intel/cannonlake end device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 on # PCI Express Port 13 - device pci 00.0 on end # x4 M.2/M 2280 (NVMe) + device pci 1d.4 on # PCI Express Port 13 -- x4 M.2/M 2280 (NVMe) register "PcieRpSlotImplemented[12]" = "1" register "PcieRpEnable[12]" = "1" register "PcieRpLtrEnable[12]" = "1" |